Manufacturer question about solder mask

[Rene_Poschl]

This thread might be useful for you: (It gives a lot of details about the problems with thermal vias when using a reflow process.)
The magic starts at about post 5

A help with QFN footprint with thermal vias and solder paste

are you looking for a Paste mask over vias? Is that any doc that has suggested that? if you look at TI manufacturer QFN layout guidelines www.ti.com/lit/an/sloa122/sloa122.pdf you will see they suggest solid vias [image] and stencil without a keep-out Paste zone [image] NXP suggests eventually to tent vias, but this is controversy among manufacturers [image]