I am trying to make an SDR based on the HackRF project, but uses an FPGA instead of a CPLD. I have sent the manufacturing gerbers to an outfit based in Taiwan. I received a mail from them that I’m finding difficult to parse.
We noticed that, in the Gerber file, all the SMT pads are now all solder mask open(i.e. the SMT pads and these vias within the SMT pads will be free of solder mask.) there are no solder masking at the bottom side, which would result in solder flowing though these vias to the bottom side during the SMT process.
The SMT pads in question have exposed center pads for ground, in which we have placed thermal relief vias to complete the connection to ground layer as shown below:
The via holes themselves are through hole pads with B.Mask option selected among the technical layers, and the clearances set to global. Please help me understand this, and how should I proceed? Also I thought selecting B. Mask for the through hole and setting mask to global would put a solder mask there.
This thread might be useful for you: (It gives a lot of details about the problems with thermal vias when using a reflow process.)
The magic starts at about post 5
Also, with respect to the exposed pad of the MAX2837, the datasheet states …
Exposed Paddle. Connect to the ground plane with multiple vias for proper operation and heat dissipation. Do not share with any other pin grounds and bypass capacitors’ ground.
Thanks for pointing that out. I have corrected it. I was thinking of ground in abstract terms back then, which why I thought it made no difference and simply connected the ground pins to it. Very unfortunate that I didn’t go back and correct it once I knew otherwise.
The question of “How do I define a solder-mask tent over the vias on the back side of the board?” is rather straightforward: edit the parameters for the pads you are using as vias.
The real question is, “SHOULD I define a solder-mask tent over the vias on the back side?”. The answer to that is, “Have a serious talk with the manufacturing engineer responsible for populating your PCB assembly.”.
Read through the discussion linked by @Rene_Poschl. It mentions several factors to consider. I’m not a manufacturing guy, but I’ll share what I recall from conversations a few incarnations ago (circa 2003).
A via that is open from top to bottom can wick solder away from the thermal pad, create solder bumps on the back side of the board, and make a mess (loose solder balls and flux spatters) in the reflow oven. On the other hand, the plugged via improves the thermal coupling between top and bottom copper fills and provides an easy way to visually confirm that there is a good solder joint between the IC’s thermal pad and the top copper pour.
A via tented on the back side avoids the problems mentioned above, but air trapped in the via can expand, lift the IC off its footprint, and create poor or missing solder joints.
Your approach to the problem will be influenced by the reflow process being used as well as the type of solder and flux. The manufacturing guys may ask you to adjust (either increase or decrease) the diameter of the via holes, or the paste pattern. The Project Manglers never like to hear this, but you may end up running a couple batches of a few dozen boards that get a very careful inspection and testing, in order to determine the best approach in your particular situation.
