Direct heatsink copper core pcb
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3
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327
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June 14, 2025
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Issue: Pins Not Filled in KiCad PCB Editor – How to Fix?
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3
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217
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June 14, 2025
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Netlist issues with Net-Ties
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19
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385
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June 13, 2025
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Multi-channel does not copy filled zones associated with reference nets to target rule areas
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9
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261
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June 13, 2025
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Walkaround getting stuck on some parts?
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4
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239
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June 13, 2025
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Compare Footprint with Library, for whole PCB
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3
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301
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June 13, 2025
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FEM Voltage drop simulator
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36
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2904
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June 13, 2025
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Editing copper pour
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6
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246
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June 12, 2025
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Pins of two footprints overlaying but no DRC error?
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14
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495
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June 12, 2025
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Gerber output without solder mask on tracks
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6
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228
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June 12, 2025
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Adding solder mask to a pad
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13
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551
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June 12, 2025
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Magnetic points not snapping with copper zone
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3
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260
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June 12, 2025
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Importing KiCAD-generated Gerbers into Ansys HFSS
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2
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341
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June 12, 2025
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Blind/Buried Via About Help
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10
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236
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June 11, 2025
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Hilighting net in PCB layout by name
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3
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181
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June 11, 2025
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Kicad9, no right inport from eagle cad
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8
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328
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June 11, 2025
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Is it a matter of tuning length of a differential pair?
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2
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381
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June 11, 2025
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Regarding Clearances
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5
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346
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June 11, 2025
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Enforce minimum connection width in filled areas
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5
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536
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June 11, 2025
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Vias through different layers
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3
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177
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June 11, 2025
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OpenCASCADE error while exporting step file
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8
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465
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June 11, 2025
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Novel (?) Combi Footprint and symbol using it
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8
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426
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June 10, 2025
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Unable to get Multichannel working
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9
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253
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June 10, 2025
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Topology mismatch not allowing Repeat Layout function
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10
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799
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June 10, 2025
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nRF52840-CKAA WLCSP-93 via in pad help
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3
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244
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June 10, 2025
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Footprints and Symbols source?
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4
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564
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June 10, 2025
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Warning for Copper connection too narrow
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11
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523
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June 10, 2025
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Symbols and footprint kicad ver 6+ files for RV7L020GNTCR1 (RoHM semiconductor)
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2
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273
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June 9, 2025
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Is there a "standard" resistor/capacitor footprint?
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26
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1524
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March 14, 2025
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Getting tolerances/clearances from Altium board
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8
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436
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June 9, 2025
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