I hereby certify that I am not simply asking someone else to design a footprint for me.
Hi! I’m new-ish to board design and have been having issues trying to get my solder mask constraints set up. I’m using PCBWay’s standard service but with 4/4 mil for traces and 0.2mm holes. I have solder mask expansion set to 0.0508mm and constraints pulled directly from PCBway’s constraints site.
However! Irrespective of these settings, the pads on my footprint have giant outlines that the internet seems to identify are solder mask related, and DRC is complaining that "Front solder mask aperture bridges items with different sizes.
I have verified footprint and footprint pad settings have all solder mask and paste fields unset, meaning they should be using global board defaults, which shouldn’t be that large, and aren’t affected if I change the values as far as I can tell. The connector for those curious is https://www.hirose.com/product/p/CL0480-0369-0-51. The footprint I grabbed from easyeda, I have inspected it and it seems fine, I can provide that if it would be helpful. But it’s worth noting these outlines do not appear in the footprint editor, only in board view.
The red lines around the pads are normally an indication of the copper to copper clearance of the pads, and should not overlap with copper from other nets. The “solder mask aperture” may be a separate issue.
Best way to diagnose is if you upload a stripped version of your project, With just that schematic symbol, and something to connect it to (a few resistors), it does not have to be a “working” schematic. Just make a copy of your project and delete all the distracting stuff.
Thanks for the info! The copper to copper shouldn’t be that big–I have 2 mil spacing set in constraints and the radii of the outlines are definitely more than 2 mil. Maybe hole clearance? Vias probably shouldn’t be that close.
I don’t have time at the moment to do the read 30 articles thing, but my project is on GitHub in full:
That should be enough to help, alto a simplified test project is a little bit easier to diagnose. Unfortunately I’m still on KiCad V8 myself, and your project if V9, so I can’t help.
On a sidenote, in the directory Mipi-mapper/v0/e90-dsi-split-backups there are 24 copies of older versions of your project. That redundancy is a bit silly when you use GIT. There are some gitignore files and tutorials floating around for setting up GIT for KiCad.
We can still attempt to find it another way. Pad clearances can be defined in several different places. Normally they come from the board setup (net classes, custom rules), but overrides can also be set in the footprint or for individual pads in the footprint. Are you familar with those options? (If not, read the manual).
Yea, checked this first (thanks manual and ChatGPT for suggesting this early on ; ) )
Footprint and pads are empty or have copies of my global values for clearance overrides, so shouldn’t be anything there. My global values should be good.
Re: netclasses, I have been using a pre-defined size much smaller than and instead of the netclass width–maybe I need to adjust netclass settings as well? I will check on this, thanks for the tip.
Oh wow, that really dropped it. Definitely was the net class defs. The outlines got a lot smaller too. Thank you so much! I will play with the settings and see what I can do.
