4)I press 6 and in walk around routing option an nothing never start to route
5) The differential pair propierty is w=0.265 gap=.1 clearance=.1
90 ohms for a 4 layer 0.2 first prepeg.
6) i change the board to 0.1mm first prepeg, and with the values w=19 gap=0.2 cleareance=0.4
I get error to the pin of the chip
7) I change the cleareance to 0.1, and the route didnt start without explicit reason
8) i change the cleareance to 0.3 and i can route.
IMHO Now the problem is that a cleareance of 0.3 is wrong because must be 2x W 0.4 and must be tolerated the chip connection.
Best Regards
Dear,
I dont believe on magic. Normally i dislike when the tools don’t do the work without explanation. Because with no explanation is more harder found a solution. Obviously, in this part we are talking about one bug.
In second hand, With the right cleareance, kicad cannot work because the right cleareance is 0.4 but i need put 0.3 to do the tracks. Here is another bug.
In third place at same way that you broke the impedance matching when put vias to layer switch and the program tolerate this, the program must tolerate when you connect to the chip QFN with a minimal pin separation.
To end i didn´t find a tool to draw the differential pair (both traces)
Arthur C. Clarke, a very renowned science-fiction writer, once said: “Any sufficiently advanced technology is indistinguishable from magic.”. I don’t believe this applies to KiCad (or its differential pair tool). It’s just technology and as such it may have bugs. Unfortunately, in order to locate and fix them, we cannot use a crystal ball - as you said, you don’t believe in magic, neither do we. Therefore, would you be able to share a minimum design that demonstrates the particular clearance issue you’ve experienced?
Thanks. I removed all diff pairs from the board and routed them again without any issues (walkaround mode, clearances set as in the design rules). Do I need to do something special (change some DRC rules?) to make it stop routing?
Yes try increase the cleareance for USB to 0.4mm (double of track width).
Or try use the tracks required for 4 layer with a prepeg of 0.2mm (w=0.265 gap=.1 creareance 0.5) In J301 didnt start routing at all
so the router will not be able to place anything there without violating the clearance in the first place. The diff pair gap setting does not override clearance settings…
This is one of the points !! I didnt made the chip (usb HUB), i didnt make the USB spec ( 90 ohms, differential pair), and i didnt create the rule about cleareance to avoid external capacitance. But i need play with it and adapt to work with it. If the life give lemons then make lemonade.
In the same way that kicad tollerate broken of gap in certains circumstances, kicad must tollerate the connection point to the chip
But in separated channel of this tolerance, the program must inform to the user about the reason why i cant route, and allow violate the roules (press CTRL+click to continue)
It seems you might have a small misunderstanding of concepts:
Clearance is the minimum allowed distance between that net and any other copper on the board. Usually you set this to the smallest value your manufacturer can produce (0.1mm in your case). If you set this to 0.4mm it wouldn’t make sense because you’d get violations due to the separation between the pads in the footprint.
Diff pair gap is the required separation between the + and - tracks of a differential pair. This is probably what you want to set to 0.4mm.
Try setting clearance to 0.1mm and diff pair gap to 0.4mm. The router should then behave as you expect.
Dear Qbort.
I know what is cleareance, thanks. But is exactly the problem. A impedance controlled track (ex USB) need a minimum distance to another copper of wide x 2.
Obviously this requirement is not possible on this USB chip, but microchip sell a lot of chip of this model, and i am forced to use it.
Put a cleareance of 0.1 i can go inside of chip, right. But in the rest of the PCB i need 0.4.
As you see, Altium has the tolerance for the chip connection.
For example cadence say 3x: “Keep the diff pairs isolated from other traces. This is often done by specifying a clearance of three times the normal trace width spacing.”
And please don´t forget the PRINCIPAL point, inform to the user “what is happening”, don´t route at all without explanation is a error. Don´t route at all without possibility to continue marking “i know what i am doing at my risk” is another error.
What I would normally do in this case is to route single tracks from the chip a small distance away with the smallest clearance, then create the largest clearance and from there use the differential pair routing as desired
It seems that the way Altium works is pretty advanced, but it is not how currently KiCAD works, you may add a desired feature in Gitlab and if enough people upvote it, it may get implemented.
