Post-v5 new features and development news

There is a new automatic project backup feature:

  • Enabled by default, can create backups every time you save a file
  • Optional creation of backups when auto-save is triggered (disabled by default)
  • Limit on total number of backup files and total backup file size
  • Limit on number of backups to keep per day
  • Setting for minimum backup interval (for example, if you like to hit Ctrl+S every 10 seconds but don’t want a new backup file every time)

How does it handle schematic files which are not in the project folder or its sub-folders? Is there a possible collision when two projects are using the same schematics file?

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It does not, same as the existing project archiver (which uses the same code). Schematics must be included in the project folder (or a sub-folder of it) to be backed up.


Thanks to Jon, we can now hide ratsnest lines for a net. Select a board item belonging to a net (most often this would be GND or some other ubiquitous net which makes it difficult to discern other nets). Open the context menu and you’ll see Net Tools and can hide/show the selected net.

There’s also some backend support for coloring nets, but there’s no GUI yet.

EDIT: I created a new thread New Net Tools in pcbnew 5.99 because I can foresee this will raise comments, questions and feature requests.


Small warning: I didn’t post about this yet because there may still be a bit of churn in how exactly this works. It should be safe to play with though :slight_smile:


Net Classes can now be assigned in Eeschema. They can also be used to color/style the wires & busses of a net. (And of course they feed through to PCBNew Net Classes.)


Will the Backup exclude other ZIP files to prevent ever expanding ZIPs?

Yes. In fact, there is a fixed list of file extensions that will be backed up:


Will it be possible to display the net names on the schematic or just assign them? Could you automatically just apply labels as net names?

I’m not sure I’m following. Net names are already applied by labels.

Net class assignments are what’s new. Net classes are normally applied to more than one net name.

We’ve talked about how to visually indicate net classes on the schematic.

  1. The current way is to use the net class colors and line-styles. Negatives are that they might not work well for very large netclass sets; positives are that they appear in plots, print-outs, etc. and have historical precedent.
  2. We could also support annotations (like the net names shown in PCBNew). Positives are that they’re easy to turn on/off en masse; negatives are that they won’t appear in plots, print-outs, etc.).
  3. We could have a mechanism similar to labels. Positives are that their placement, orientation, etc. is under the control of the author; negatives are that they’re harder to edit en masse and they can be visually noisy.

I’d love it if we could get by with just (1), with a slight preference for (1) + (2) if we can’t. I think Jon has a preference for (1) + (3).

Please continue the discussion in the dedicated thread: Net classes in Eeschema (5.99).

It’s now possible to create a new net in pcbnew with Inspect -> Net Inspector. It can then be assigned to a pad in the pad properties. The change can also be fed back to the schematic with Tools -> Update Schematic from PCB (with more or less success).

This is an answer to long standing need for easier PCB-only design (WireIt plugin has been used for it).

Again, I opened a new thread for discussion: Creating nets in Pcbnew (5.99).


Note: this is my interpretation and doesn’t necessarily reflect the development team’s intentions accurately, so take this with grain of salt.

Until very recently many issues in gitlab had the milestone for v6 even though it wasn’t certain if someone would implement them. Now there’s milestone 7.0 and some issues were moved to that:

There are now three feature development milestones: 6.0.0-rc1 , 6.0 Feature Freeze and 7.0.

6.0 Feature Freeze is for new (major?) features. For each proposed feature it must be decided if it actually will be implemented for 6.0, and now it seems to be the time to make those decisions. If nobody hasn’t volunteered to implement a feature, it won’t be in a condition to be included when the feature freeze moment comes, and it can’t be set to that milestone.

The rc milestone is mainly for bugfixes and other smaller changes. They must of course be ready when 6.0 is finally released.

I see 7.0 as preliminary in nature; ATM it includes only old feature plans which were postponed because of lack of manpower. They can be postponed even further, or maybe there will be 6.1 where something can be implemented.

6.0 Feature Freeze and 7.0 should correspond roughly with KiCad 6.0 Roadmap and KiCad Future Versions Roadmap but I haven’t checked how up to date those are right now.


This is essentially accurate. Our plan is to announce the feature freeze in September and move on to polishing the features and fixing bugs.

This is also why the rc1 burn down chart doesn’t look good but the FF chart looks promising.

We’re pushing other ideas to the 7.0 milestone as a convenient place to store them. Once 6.0 is released, we hope to sit down (maybe at FOSDEM if it happens) and hash out plans for 7.0 features.


There’s discussion going on about dropping support for 32 bit Windows because the build system is dropping it: No decision yet, but better be prepared because it will eventually happen some day.


There cannot be many PCs around with 32 bit hardware
For some reason some corporates have hung on to 32 bit Windows due to compatibility fears with old custom software.

But I bet that a significant proportion of the 6% downloading 32 bit could actually run 64 bit

KiCad source code has new build dependencies, see the announcement by Ian: If you build from source and it complains about something missing, try these (lemon; GTK3 on Linux).

EDIT: Thanks, marekr – it’s not in yet, it’s being tested first.

EDIT later: the plan was changed, no need to install lemon, see

It hasn’t been added yet

You can now access the symbol and footprint library editors without having a project open


Geographic reannotation, i.e. reannotating based on the component positions on the board.

Tools -> Reannotate PCB

EDIT: separate post here: Geographic Reannotation Now Included in PCBNew