Net classes in Eeschema (5.99)

Net classes can be defined in eeschema. Net classes are now in both pcbnew and eeschema, in the board settings and schematic settings respectively:

Jeff told about it:


To everyone follow, the propose of 3 can be understood in

Also for reference although I didn’t yet mention it in that issue: Jeff and I had talked about one option being to give labels their own “fields” (i.e. the same way a component has fields) that can be hidden or shown. Netclass would be one of these fields.

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I’m not testing the 5.99 nightlies, but I have a question about the colors. Is it free-form color chooser or just a list of colors? I hope free-form, but if it is a list of colors I hope the 10 standard resistor color codes are all represented. (Granted, printing yellow on a white page can be challenging…)

Also, I tend to use color coded test-points (which are available in the 10 standard resistor color code colors) for different signals. Does it make sense to allow some sort of hierarchical net classes? For my example, I would have a parent netclass for signal that defines the width and spacing and a default color. Each child would only change the color. That way if I decide that I want to thicken or thin all my signal routes I only have to change the parent net class instead of multiple differently colored signal net classes.

Is this a complicated enough suggestion/request to warrant its own github issue? Or am I just crazy?

I would like to use eeschema net classes to communicate design requirements from the schematic to PCB layout. Even in a 1-man shop it is good to have your own design notes available to help constrain your layout design. In a 2-man shop (schematic → PCB layout) it is important/imperative to communicate design rules/requirements with the ability to easily (and consciously) override in PCB layout as necessary:

Power: needs more copper (thickness and/or trace width) to carry current, also where flood/fill is used
Low Noise: Clearance from noise generators like switching supplies, phase locked loops (jitterators), other digital logic (noise generators) for sensitive analog front-ends in both synchronous and asynchronous designs
High Speed Design: Can’t cross gaps in copper planes or reflections and signal degradation occur from impedance mismatches
Differential Pairs: must be routed together and length tuned to avoid signal degradation especially when routing around bends, vias, parts other obstructions (USB, HDMI, etc.)
HS Bus Groups: Where clock and data are running fast enough that edge timing and rise times are critical for signal edge alignment and noise management (think DDR memory designs, HDMI, etc.)

I spent this morning looking for information about how I might use KiCAD 5.1.6-1 release build Net Classes to communicate these necessary design rules from schematic generation to the PCB layout phase of a project to help me maintain my own sanity in non-trivial designs. Otherwise these things must be documented and check-lists prepared/maintained manually in LibreOffice type documentation. This is as much of an “option” these days as rubbing sticks together to make fire.

My sense of the current state of affairs is this is the direction KiCAD is headed, which is fantastic. Seems like there isn’t much clarity (some confusion) about what problems are being solved from this and other postings in the forums. I hope this short list helps provide clarity from a must have for engineering performance reasons as opposed to artistic esthetics (colors) which might enhance documentation clarity for error reduction, also important, but secondary to performance needs.

If what I described isn’t clear enough, I have three different books on the subject I can recommend.

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