Beginner's questions before sending for print

Hello everybody,

My project is a small board containing an esp32 and some sensors (5v, less than 0.5A in total everything included)

I’m designing my very first pcb and I have some doubts so I would like to have your opinions before sending my files to jlcpcb:

  1. Is there a generic rule to define the minimum isolation ? Do you think leaving it to 0 is a bad idea ?
  2. Since I moved to Kicad 7.0.2 I’m getting this new error:

It seems to throw that error because there is a connection to a zone on only one side but as there is a also a track, I don’t think it’s an issue. Am I wrong ? Is there a way to tell Kicad that the track is enough and that it is not an issue ?

  1. Also if there a way to tell kicad to connect to copper zone in diagonal ? In the screenshot from point 2, I think I could have two connections to the copper zone if I placed them in diagonal.

  2. When using a zone to connect pads to GND, is it ok to have only one connection (one link) between the zone and the pad ? The error from above make me thing that maybe it’s not enough, is there a rule to follow ?
    I don’t get what is the difference between a trace of 0.5mm and a connection to the copper zone (connection of 0.5mm). Why one trace is good and not one connection to a copper zone ?

  3. I would like to place gnd connection from underneath the BME688 sensor and I’m wondering what would be the best between a zone and tracks ?

    or this

  4. Trace width: I wanted to be sure that my traces are wide enough to not cause any problems like voltage drop or heating too much. So all my traces (except the ones for small smd packages) are 0.508mm width. Do you think that it is a good idea ? What would you recommend knowing that it’s for 5V with less than 0.5A (for the total of everything).

Sorry for all those questions that sound probably obvious to you, it’s my very first time, I probably did many mistakes without even knowing.

I’m thinking to ask if someone wants to take some time to quickly review my design and tell me if I did big mistakes before I validate the order (I’ll pay for that of course but as it’s a hobby project, not too much ^^)

Thank you all for your help :slight_smile:

I think that minimum insulation has no influence while designing PCB as isolations specified elsewhere works. I have never used JLCPCB or any other international source, but my local PCB manufacturer wants to know what is minimum isolation at PCB. They can manufacture PCBs with minimum track width of 4 mils and minimum distance (isolation) also 4 mils. It is top of their possibilities. Manufacturing PCBs with no so demanding requirements is simpler. I typically use 8mils track/8mils space. To be sure that in any point at PCB I not violate what I will then specify when ordering I just set my minimum to 0.2mm (it is about 8 mils).

When you use zone than you want something to be solid connected to it. You use thermal spokes only to help you soldering. If there are 4 spokes then from electromagnetic point of view it is close to solid connection - current can flow in any direction. If you have less then 4 spokes the connection is less ‘solid’. As you have set that your minimum is 2 spokes than if somewhere there is only one than DRC report it as an error. It is you who should know your circuit to know if it is problem or not. If it is not a problem then specify 1 as minimum or set to ignore this error at all.

I think in V7 somewhere it is. Never searched for it, but in last few days I sow it in one thread (don’t know its title).

Only what I can say is: It depends.
I think in your case it is ok.

Zone (even with no thermal pad) allows for better heat transmission from IC. I suppose it is don’t care in your case.

I use 0.25mm tracks for signal lines and wider for supply lines. For currents up to 100mA I use 1mm tracks, but if I have currents around 300mA I am trying to have 2mm tracks whenever possible.
Remember that copper thickness at PCB is typically only 0.035mm.

Me too, I think it was this one . . .

It is often a good idea to have one layer as a ground fill. Even with just a two layer PCB. So you don’t have to route every GND line manually. If that pour gets interrupted, you can easyly stitch it back together with a short track on the opposide side.

Mixed analog / digital or sensitive analog designs (I hear the audiophiles already shouting!) require more thinking regarding to a ground fill. But as a rule of thump, it is better to have a plane than single traces. Again, YMMV!

Thank you for your answers, it helped me to understand better :slight_smile:

Thanks it’s exactly what I was looking for !

I’ll keep the zone, thanks

I was far away from that, good to read your way of working. I made my power tracks larger.

It is was I did, I even have a ground zone on the two sides :stuck_out_tongue: I forgot to mention it in the first place. Thanks

From EMC point of view ground fill should have no gaps. Each signal has associated with it return current. The higher frequency (the shorter rise/fall times) the return current travels no the shortest way back but prefers to travel just under the line with signal. Whenever signal line jumps over gap in GND fill the return current have to travel the longer way what makes the area surrounded by current much bigger and the same way EMC emissions higher and the sensitivity of the circuit to disturbances also higher.
So the best from EMC point of view is to have one continuous GND fill. All my 2 layer PCBs have no signal lines at bottom as to have continuous GND.
An example of such design I shown some time ago:

If you want to read more about EMC see links I gave some time ago:


That’s why I said he should stich. You often see massive stiching on HF PCBs.

And you are sure he understood it well?
Your sentence:

Can be understood that if other tracks make GND fill to have several not connected islands than using a short track on the opposite side you can connect that islands together. This has not a lot with ensuring the return signal path just along the signal track.

That’s your interpretation. Simply set “Remove islands: Always” (the default).

And that’s your interpretation. I was speaking about islands that are connected to at least one GND pin so not removed by this setting.

I’m not sure to understand that concept, it’s kind of advanced and I’m just beginning. I’ll try to read more about that. But anyway, I need to use the back layer to put some traces, otherwise it’s impossible to route all my traces. I’ll try to reduce it to the very minimum.

My pcb looks like this:

front layer:

back layer:

(All the non isolated traces on the back are gnd too, so not breaking the continuity)

Do you think that it will cause real problems to have those traces on the bottom ?

You didn’t considered using 0Rs to jump with one track over others :slight_smile: (with 1206 0R you can jump over 4 or 5 tracks).
First approach is just to use both sides for tracks (no zone fills). We did our PCBs that way in 90s until we had a problem with device that hang-up each spring and autumn during storms. It happened only at one of our 100 installations all over the country. It was in the highest place locally and many lightning strikes there. PCB design was not the main source of problems but collecting all information I learned (by the way) that PCB should be better designed.
Second approach is to use zone fills the way you have at your PCB.
Third approach is to limit openings in GND zone to very small ones. To just cross tracks you need only short track section. In most cases it is no problem for electrons if track has a complicated shape just to make such solution possible.
Fourth approach is to replace such crosses with 0Rs.

I think third approach improves a lot PCB EMC properties over second approach.
Fourth gives even more but there is no big difference between third and fourth.

I typically don’t need a lot of 0Rs because to limit VCC current pulses at most digital wires I use small resistors (like 100 ohm). If digital output switches the IC needs a current pulse to reload connected to that output tracks (if you have GND fill track capacitance is bigger) and other ICs inputs. The faster switching the higher current pulse needed. Thanks to such resistor only the own output capacitance have to be reloaded at once and rest slower (100 ohm * 10pF = 1ns - not important in most cases). This reduces spikes a lot. This resistors helps me also to not need to use second side for routing.
Limiting current pulses is also good for PCB EMC properties.

I use fourth approach since I was solving that problem with storms. Later we (Poland) joined EU and EMC tests suddenly became mandatory. When I went to lab to test our devices they were surprised that each one passes all tests with no problems.


I didn’t look at this carefully, just a general remark: you should stitch the front and back GND layers together with vias. Especially every sharp corner of a fill and then other corners and near all fill edges. It doesn’t hurt to have more than enough, there’s room for hundreds of vias. Like this. An arrow points to a place when you can move a track a little bit to fill more of the empty space.

All these vias give continuity for the GND copper. Otherwise you loose the benefit of copper pours because the current must find its way through longs paths. (EDIT: this depends on the frequency of the signals; see posts above which I read only afterwards. DC likes to find the shortest route. In any case it’s good to connect the front and back layer fills.) Without vias you also will have potential antennas, like here:


You can remove narrow antennas by moving some tracks closer together. In this case moving the front track above the GND slit (pad 4) downwards could even give room for more useful stitching vias.


Oh thanks, I never thought about that. It’s good to know. I’m trying to follow your recommendations the best I can, I tried to move from second approach to third one (easier compared to fourth one).

I reduced the track the the minimum I was able to. It looks like this now:

(On the image you can see multiples track that are not isolated, they are tracks for the ground. I don’t know if it’s really needed but I don’t think it can have downside to have too much ground ^^ I did it only to ensure that I have a good ground connection for pads with not a lot of connections to the ground zone. If you think it is stupid, tell me :stuck_out_tongue:)

It’s really interesting to see the approach with 0R, I was not aware. I’ll give a try with that in my next pcb design for sure. This one is my very first design so having a pcb that is working and doing what it should would already be a first victory for me :smiley:)

This is also a very interesting information. I tried to clean up a bit the back side until now, and I’ll tackle that right after. If I understand well, the more via I have the better, is that statement correct? I think I got the idea of having via at all possible places where a current could wants to go to make path as straightforward as possible. Thank you for pointing that out :slight_smile:

Disclaimer: I really know nearly nothing about electronics (hyperbolically speaking, for the sake of making sure you know you should consult some more knowledgeable source).

Within limits of common sense. Don’t add as many vias as you could with the manufacturer’s hole to hole clearance. :slight_smile:

Vias make the GND copper as continuous as possible. You could think it this way: one purpose of the plane is to make sure any two points belonging to the ground (or some other plane) have as small difference in potential as possible. The longer the shortest path between two points, the worse. Adding vias shortens the route.

When there are high frequency voltages/currents/electromagnetic fields things go complex. In GHz range it turns into black magic. Sharp corners or long protrusions can act as receiving or transmitting antennas. Copper areas which may work as antennas can be removed by adding vias connecting to the copper fill on the other side of the board.

Jitter | Electronic Design and Consultancy (a plus for nice screenshot illustration clearly made with… guess what)

Ground Plane PCB: A Return Path for Circuit Current and Components

Understanding 2-Layer PCB Ground Planes | PCB Design Blog | Altium

Thank you for your answer. If you “know nearly nothing about electronics”, I probably know nothing :stuck_out_tongue: The concept of return current loop seems to be a bit difficult to understand
as I’m just beginning as I’m lacking some basic knowledge… I’ll read more and try to understand but for now I will try to do something simple to start with.

What do you think about this:

Do you see big mistakes ?

Just have in mind that current always flows in a closed circuit. For each current flowing from your source to destination the loop have to be closed someway. You have a control of way it takes from one IC output to other IC input by routing track. But you have less control of the way back. The smaller the surface surrounded by this circle the better. High frequency current helps you to minimize that circuit as return current prefers to return just under the track so the PCB thickness is what decides of circuit area (look at PCB from all sides as electromagnetic fields don’t follow our way of looking at PCB in editor).
If you have 4 layer PCB with GND and VCC zones at inside layers than whenever fast signal track jumps from top to bottom then near that via you should have a capacitor connecting VCC with GND as return current travels through the nearest to track zone and at that point it have to jump from one zone to the other. If it have to find the long way then the area we try to minimize is increasing.
If you want to be good in PCB design read the articles I have mentioned previously.

It is much, much better than previous.
I don’t know your circuit. If it is purely low frequency than it can be not very important, but I simply prefer to do everything the best I can.
If it were my design I would not accept the big openings in GND zone for a series of pads. Clearance have to be smaller or pads have to be smaller (or oval). The task is to allow zone to pour between all the pads (I typically use 0.25mm zone clearance).
Make fills at top to function as part of bottom zone. They should be connected along their all borders (add some vias along PCB border) and I would also add randomly some vias inside bigger fills at top. I don’t have other arguments for it beyond that I just feel it is better.

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thank you for the explainations about the return current loop :slight_smile: , It helped me a bit, still not 100% clear but I’ll continue to read articles about that. It seems to be an important topic, I’ll try to understand that !

Good :slight_smile: Thank you :slight_smile:

Really interesting remark, I did not think about that ! I’m now trying to improve that point. (Don’t hesitate if you have other points that I missed like that one, your precious remarks are very appreciated)

I lead me to one more question :stuck_out_tongue:, what do you think is “reasonable” in term of clearance for a pad ? Because I don’t really know what is acceptable, I suppose I can not put a clearance of just 0.2mm for all pads. Isn’t it a bit risky to have ground zone that close to pads even (magnetic field can maybe cause unattended alternation in signal?). Do you have an opinions on that ?

I was already able to improve a bit TH pads from the central footprint (by changing zone clearance and pad dimensions). It looks like this:

But for the TH pads on the left I don’t understand from where to clearance is coming from. I checked all the settings I know and it seems to still be bigger.

Example with TX1:

  • pad
    Capture d'écran 2023-05-01 151647
    We can a clearance of 0.4mm and I don’t find where this come from

  • Design rule constraits:

  • There is not pad clearance on the pad itself

  • TX1 is using the netclass “Signal”. The netclass is configured to have 0.2mm of track clearance (There is no option to configure clearance onfy for pads as far as I know)

  • The zone is configured with 0.254mm of clearance

I have the impression that there is one 0.2mm clearance around the pad coming from the netlist (marked with the yellow border) but where is coming from the other 0.2mm of clearance is a mistery to me ^^ I can edit pad properties of all pads to put a “pad clearance” as I want, that is working fine, but it seems to be a bit hacky and it’s probably not the right way of doing it.

In all cases it is a really good advice that you gave me. It seems way better now :slight_smile:. I just need to figure out what is an acceptable clearance between pads and groud zone (thinking about 0.2mm, but it’s maybe not enough).

Current result:

Many thanks for the time you are spending on helping me :slight_smile: You saved me from lots of problems that would be discovered too late (after having ordered the pcb) I now understanding the importance of having a good ground zone ^^

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I assume the GND zone has the “Power” netclass, which has a general clearance of 0.4mm.

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