Out of curiosity, I checked my current PCB that uses a lot of zones. Nowhere can I set the power netclass. Still they are GNDA, GNDD, 5VD, … with a PWR_FLAG in the schematics. And the clearance is 0.2 mm as in the zone properties and verified with the ruler.
To the OP, it looks to me, as if the clearanc is the same for your zone (look at the vias). This should not be the solution, but maybe you try to set the termal relief gap to 0.254 mm.
Yes the GND is using Power netclass but I don’t think it is the problem as in the example I’m taking TX1 that is using Signal netclass.
I already tried and it does not change anything. There is a clearance of 0.4mm around pads using “Signal” netclass. I really don’t get from where the extra 0.2mm comes.
If GND takes 0.4mm clearance from Power netclass settings that means GND net to any other net have to have clearance 0.4mm. So when you have GND zone it have the clearance of 0.4mm to anything else.
But GND pad to GND zone have not clearance from Power netclass. Clearance don’t works from net to the same net.
With GND pad the 'Thermal relief gap works that happened to be also 0.4mm.
So that way you made all pads to have 0.4mm distance from GND zone.
Reasonable clearance depends on voltage difference between nets. If you don’t have higher then 12V voltages at your PCB then there should be no problem to have 0.2mm clearance.
For reasons of historical habits I use 0.2mm clearance for Default net class and 0.25mm for zones. In past where PCB factories had no electrical check of manufactured PCBs it happened sometimes shorts between nets and the long distances of different nets being close one to another is between zones and other tracks. So to reduce the risk a bit I used (and still use) bigger clearance for zones.
For me VCC and GND also belongs to Default netclass. I just manually select track width when routing.
I add the second netclass when I have nets with higher voltages (like 24V or PoE 48V) just to specify clearance 0.4mm.
Look at your picture pad 16 +5V. Track protrudes beyond the pad. In such case I am trying to have last, very short segment (whole inside pad) with lower width to not have that effect. KiCad doesn’t help in it. In fact, it does everything against such a solution. When you go inside pad it jumps to its center. Zooming in doesn’t help. When the pad occupies the entire screen your cursor will jump half the screen realizing the snap to pad function.
I have reported 4 or 5 years ago that snapping should be limited to some distance in screen pixels but it looks that it is only my problem.
Switching on and off snapping is not the good way as I want that short track inside pad to snap to pad center (helps in case of dragging a footprint).
As an exercise find the way how to do it 
Since I use KiCad (2017) I have to do it with almost all pads at power tracks as tracks are wider than my SMD pads they are ended at.
Then that is the problem. Clearance is typically computed between two different nets, in this case between GND and TX1. The larger value wins.
It make sense, I don’t know how I missed something that big ^^ I now understand your previous answer 
Thank you for clarifying that
Yes I totally missed that point. It was obvious thought ^^ Now it’ s clear, thank you for that very clear explanation
The maximum voltage that I will have on that pcb is 5V. I’ll follow your recommendation and set 0.2mm for the power netclass. That’s answering my 2 questions (0. 4mm clearance + acceptable clearance). Again your answer helped a lot 
And that’s cool, I was pretty sure that there was a feature in kicad for that, I searched for more than half an hour yesterday ^^
I think I found a way, I just created a track the same width as the pad and placed if from left to right. I just had to ignore the warning that the track is not connected. Is it how you do it as well ?
(the pad is hidden on the image to make the track visible)
I am a born teacher
No.
When you start from that pad with thin track width then you are able to do a short segment (going toward direction you want and after fixing that segment (being still inside pad) you can change width to one you want to use for the real track. As your wide track starts not at the pad center its rounded end can be whole inside a pad.
But I use it for SMD pads that are rectangle (rounded rectangle). Doing it with oval track you will probably not get equal width at the exit of the pad, but I would not consider it as a problem.
So when I am routing a wide track toward my pad I finish it some distance from the pad and then I start routing from that pad to be able to do that thin segment inside.
I have to do it practically with all pads at Power nets (fortunately, power nets are in the minority). This ‘feature’ is one that I dislike the most in KiCad. But I have done what I could to have it improved (in my opinion) with no effect.
Unfortunately I have never worked in any team on software. I have never used git or any other tool like this. I feel being not enough competent to even try to correct it myself.
One eternity later… I did it !!! Removed all the traces from the back side (had to change mostly all my routes and some part positions. But I did it. Thank you all for the good advices you gave me
Top view:
I cheated a bit with the two 2512 0R (jumping over 7 traces) @Piotr As you can see, I followed your advice for that too finally ^^. At the end I’m only using three 0R and nothing on back side anymore That was an interesting thing to discover
At first I did not want to “polluate” my schematic with those 0R but I did it in way that is not so ugly (Using labels helps)
Thank you again for your help Now I just need a last check of everything (hole sizes, connections, …) and I send it for print with JLCPCB. I’m so happy that this project is finally reaching that stage Now I have to pray that I did not miss anything and that it will work as my prototype do.
Congratulations, and glad to hear it.
I hope that you understand that such restricted rules are not mandatory for PCB that (as I suppose) will not be “placed on market” and you just decided to treat it is an ambitious exercise.
Equally good solution is to use just short wires instead of these 0Rs. They can be placed at top (SMD) or little worse mounted THT (at top or at bottom). You can do special footprints for it (narrower than big 0R footprints ot narrower than big THT resistors).
I use SMD 0R as it simply is automatically assembled in the same process as all other elements and it costs close to nothing. Any hand made work is more expensive in mass production then placing even a quite a number of SMD elements.
If you hand made the whole PCB then using the wires can be better for you than using big 0Rs. Your decision.
One more opinion:
You have many tracks needlessly bunched up close together:
More a matter of taste is the top plane fill. For my taste, this adds unnecessary capacitance to all tracks and does little good - you have a solid plane already. At least you have no floating islands and all all fragments grounded using a via. If this would be my design, I’d delete the top fill or replace it with a +5 V and maybe 3.3 V fill.
I find it super strange to place two huge 0R resistors as jumpers - on a two layer board!
I’d use short bottom jumps to bridge the tracks, like you showed above (“current result”). I don’t see any harm making short cuts on the ground plane. Yes EMC suffers a bit but If I had the slightest doubt that this might cause a problem (not in your design) I’d simply go four layer. Anyway all designs that ever see an EMC lab from the inside are 4+ layers, they are cheap and two layer is just not worth the hassle unless you make millions of boards (EMC fail iterations get very expensive rather rapidly)
But also on my personal designs I relatively quickly go four layer if I feel it gets too messy with 2 layers, also prototypes (JLCPCB) are cheap. Looking at the example I showed above, this would likely work as two layer board with a bottom ground fill (fastest signals are SPI going to the right). But I had too many analog rails so I went 4 layer - problem solved.
All my designs I was with them in EMC lab they were 2 layers, but I 100% agree with you that they should simply be 4 layers. I have no analog signals and I was able to do all routing (with help of few 0Rs) on top with whole bottom being a GND fill.
I have read, not in one source, that copper coverage of all PCB layers shouldn’t differ too much. So if I have bottom 100% filled then I assume I should not left top unfilled (I just follow what I have read). With capacitance I would not thing it is very big. Copper thickness is 35um so the surfaces of the plates of the capacitor created in this way are not large. The larger are between track and fill at inner layer and the dielectric permittivity of the plate is about 4 when air is 1.
Thank you for your help
I grouped all these tracks to avoid as much as possible impacting my ground plan. By grouping them I was able to jump over all of them in a single jump.
If it can cause problems because tracks are too close to each other, I suppose it’s better to go through the bottom layer.
If I add more space between tracks, I’m force to trace a long track on the back, don’t you think it is an issue ? I tried to apply your recommendation and I’m getting something like this (just a draft):
Do you think it is better ? Or at least, less risky ? I suppose that having a long track like crossing my ground plane is not ideal, but what can I do else ? If I don’t want to group traces too close, I’m kind of forced to have a long trace to cross all of them.
Martinn have written:
You missed the word ‘short’.
Imagine the return currents for TX, RX signals. To go along your TX, RX tracks they can travel through top GND fill between them but then they have to reach right GND pins. I’m not telling it is bad design. I’m just trying to tell how you should look at it.
It will probably work fine, but as @Piotr wrote, the jumps on the bottom side would ideally be smaller. Of course if you were dragging them together, you’d bunch up the top side tracks again, so some compromise has to be made, but I’d rather go for multiple smaller hops that these huge ones. At least as long as the tracks going left to right aren’t super sensitive. Alternatively, you might be able to find better routes, for example change the left-to-right tracks to follow the route above the large 3.3V track and then going down somewhere in the region of the C6 silkscreen print. That way you might have to hop much fewer tracks somewhere in the region of JP2/JP3.
But this would be nitpicking, your design will probably work as is. It depends on how much you want to still fiddle with it and if you want to follow best practices or just create something that works.
I know of two effects:
Either way I think it is relevant for optimizing mass production yield, not too much for DIY.
As a matter of fact, you could replace those two fat 0R resistors with bottom layer tracks and spread out the tracks on either side of those bridges.
For a good layout, you have to understand what critical tracks are. Which lines carry high rise time signals and which nets could suffer from coupling? Most nets are harmless, clock or edge triggered signals might be a problem if parallel for long distances.
These days it’s not so critical anymore, as most functions are integrated in a SOC or FPGA and don’t need external clock lines. And probably gigabit serial links are not on top of your todo list.
But as Jonathan wrote, don’t worry too much, it’ll probably be fine either way.
…and not for small boards. Motherboard-sized is a different story, DIY or not.
I did a long track instead of multiple smaller one because there was no space enough to go back to the top layer between jumps. I first did a try with small bridge on bottom layer but I realized that it was also kind of cutting the ground plane like a long track.
That was exactly the point
I was busy trying to do exactly that when I read your comment It’s a good advice, it’s a lot better like that.
I’m trying to do the best I can with the knowledge I have. As it is my very first pcb design, I’m probably doing big mistakes but it’s by doing things that I’ll learn.
Thank you for the information. I’ll read more about that. For now I think I will continue without paying too much attention to that as it’s a simple DIY project and I would like to see if everything is working as it should. I’ll improve it later if everything works fine.
Yes that’s right, but as you said in your previous post, I have a lot of place on this pcb, I’m trying to do it better (without regrouping all the tracks in one central point). It would probably be better like that I suppose.
For that I have some difficulties, I’m using +5V, +3.3V, GND, I2C and UART. I’m not sure how I can identify which one are critical. You already tell me that I2C is slow and not that critial. So now the question is for the remaining tracks. Any idea how I can answer that question ? Is UART critical ? Are the power tracks critical ?
My new result look like this
Again, thank you all for all the helps you provide, it’s really appreciated
Each digital line can be a source of slope that disturbs some other line specially if they travel through PCB parallel for a long distance. The freuency of signal at that line is not important. Important is how fast slope is as in digital circuits even one pulse can damage the data. The problem is if the short pulse made on the second track is noticed by that second line or not. It is why Martinn mentioned clock and edge triggered signals. Clock line seeing even short pulse can count it as a next pulse with the result of wrong pulses count. The other problem is that the same ICs are made with smaller and smaller technology (to save money) and because of this they are faster. In 90s we used serial EEPROM. Than after some years we assembled the same device with the same EEPROM and it didn’t worked because EEPROM Out line was in paralel with its Clk line. Whenever Out changed state form 1 to 0 (if I remember well) the EEPROM skipped one bit.
You can imagine that edge triggered signal can be unintentionally triggered by such short pulse coupled from adjacent line when there are a slope at that line.
Power lines don’t have slopes so are not a source of disturbance to adjacent tracks, but fast current pulses taken by working digital circuits are disturbances propagated through supply to other ICs supplied from the same power. Analog circuits can be sensitive to fluctuations at their supply.
GND fill you have between your tracks protects them against coupling.
These are really details, but as you ask…
I2C being slow is not the whole truth. Signals need not be fast (for 100 kHz operation) and particularly the rising edges are slow as they are generated by pull up resistors. However, nobody prevents you from generating ns wide falling edges. Unfortunately the ESP32 does that, I once had an EMC fail because of too fast signals. The ESP32 has poorly documented and only partially implemented speed settings for its output pins. I darkly remember that I could fix I2C emissions by reducing drive strength, but for some SPI lines I had to add 100R series resistors. You will find that out yourself when you go into an EMC lab und until then I would not worry too much.
UART critical: Any fast edge (which seems to be the default with ESP32) will induce spikes in neighbouring lines, it does not matter if it comes from an UART, I2C, SPI, keyboard scan or power LED signal. Of course there are many more edges in an SPI clock than there are driving a green LED (unless you PWM it). UART receivers typically have noise filters, I think, so an single glitch won’t matter much.
