Thermal pad involving vias

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42

There are different thoughts as to whether smaller or larger holes reduce ‘solder theft’.

Many (the majority of?) authors claim that a small hole is best (0.2mm is around the practical limit).

However, quoting from a report entitled: “The impact of via and pad design on QFN assembly”:
Solder flow down to the via was seen for all the PTH via sizes tested in this study.
Solder protrusion onto the secondary size was seen for most of the via sizes with no solder mask ring.
The via with the diameter of 0.2mm (8mil) via with the actual hole size of ~ 0.10-0.13mm (4-5mil) hole didn’t eliminate solder protrusion.
More solder protrusion was seen for smaller sized via.
On the other hand, 0.51mm (20mil) via with window pane stencil design resulted in no solder protrusion for 1.6mm and 2.4mm thick board.

— end_quote —

Of course, the subjects of ‘solder protrusion’ from the bottom and ‘solder theft’ are somewhat different.
Maybe the 0.51mm via is stealing a lot of solder as the via hole is being filled?!

The other consideration is thermal performance of the via.
Cheap manufacturers use thin plating for the vias.
JLCPCB don’t seem to quote a spec. for this - they would need to be asked.
I read on the 'net that they may be using 18um - which corresponds to 0.5 oz copper.

So the amount of metal available to transfer heat is very small with a 0.2mm diameter via.
Increasing to 0.3 mm gives a 1.5x improvement.

My thought is therefore that, as you suggest, 0.3mm is a good diameter to use.
Larger diameters would consume area that could be used for solder paste, especially using the approach of isolation of the vias by solder mask as I have been talking about.

43

0.254mm hole and it still wicked and tilted :frowning:

44

This is one of those choices where the right answer depends on your assembly house.
My preferred PCB builder gets the power semiconductors nice and flat with no dry joints.
They make other mistakes, but not under this topic.

Filling vias would be an expensive requirement for me

45

One of my designs has four power FETs (500A) in TO-252 packages. I put an array of 15mil holes under the thermal tab, mostly for current sharing between top and bottom layers, but also for thermal performance. The vias get filled with solder paste when it is screened, and we have run many thousands of boards with no issues.

46

This is the Fusion 360 implementation of my latest thinking as what may possibly be the ‘best’ thermal pad with vias?!

Fusion360_3D_Model_SOT1172-3_A
Fusion360_3D_Model_SOT1172-3_A1193×704 140 KB

The silvery-grey is solder paste. This is sitting on top of a single large copper pad - so the principle is SMD (‘solder mask defined’).
(Ignore the lines on top of the central row of solder paste - that is an artifact of the model resulting from using the Fusion mirror function.)

Everything else is solder mask (not shown in the model), i.e., the solder mask would cover all of the thermal tab apart from where the solder mask is seen.

[Update: correction to previous sentence:
That sentence should read:
Everything else is solder mask (not shown in the model), i.e., the solder mask would cover all of the thermal tab apart from where the solder paste is seen.]

The solder mask covers the edges of the thermal pad, gaps which define the solder paste edges and even the via holes.
So they are the so-called tented vias (covered by solder mask at the top but open at the bottom of the PCB).

The basis of the design is that the solder paste is spaced a defined distance from the via holes (0.25mm from the via centres, the vias being 0.3mm diameter) - the idea being to discourage solder getting into the holes.

As recommended in AN2467.pdf and most other sources, there is a defined spacing of the solder paste away from the perimeter of the pad.
Also, defined distances between the rows and columns of the solder paste blobs (the ‘lands’).
AN2467 states that "distance between the lands should be 0.40 mm.
I am breaking that rule in my model by using the smaller spacing of 0.2 mm.
Probably it is reasonable to do so since my approach includes a lot of space around the vias.

As I understand it, the purpose of segmenting the lands is to
(a) provide gaps for gasses to escape during the soldering process
(b) make the stencil work better compared to a stencil with a single large hole
(c) avoid solder paste being over a via hole position.

The next challenge is to transfer this to Kicad as a footprint … !

47

???

Even this far down in this long thread you make the paste layer the same as the solder mask?

1 Like
48

Is a solder paste stencil with such narrow strips manufacturable and will it last in practical use, or will the squegee rip the thin segments when paste is applied?

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That sentence should read:
Everything else is solder mask (not shown in the model), i.e., the solder mask would cover all of the thermal tab apart from where the solder paste is seen.

As I mentioned, the solder mask is not shown in this model. (It was shown in the Mk I although even in that model the mask wasn’t shown at the perimeter of the thermal pad.)

My understanding is that the solder mask is the inverse of the solder paste.
In other words, where there isn’t mask, solder paste will be deposited, as long as F.Paste defines the stencil (as people inform me it does).

Is there an aspect on which my understanding is mistaken?

50

Yes, there clearly is.

For normal SMT pad the solder mask is (approximately) the same as the solder paste. and when the solder melts it pulls the leg of the part towards the pad, and it also creeps upwards to form a fillet.

But this does not work for the thermal pad. The solder can not go upward, it also can not form a fillet. Therefore you part may float on a cushion of solder, and it’s pins may float above the pads without touching them, or when the pins connect to all the pads, the part may be pulled downwards hard enough that the solder gets squeezed out from under the IC, and both are bad.

The solution is to make the cutouts in the stencil smaller then the pad. This gives the solder room to go sideways when it melts and to form a much thinner layer. The result is that the IC is lower, so all the pins make contact with the solder on their pads, and also there is not enough solder to be squezed out from the thermal pad.

51

???

Again: Solder mask is the green stuff that’s covering copper tracks and so on. I’ts neither the same as solder paste nor the inverse. The shape is often similar for SMT pads, put for thermal pads, it’s definitely different. You usually don’t want to apply solder mask to the paste-free areas of a thermal pad. You want to have clear copper space where the solder can flow to.

52

@paulvdh But this does not work for the thermal pad.

Doesn’t AN2467.pdf “Assembly guidelines for PwrQFN (Power Quad Flat no-Lead) packages” (51-page NXP recent document on the subject) detail that the approach I am working on is a valid approach?
[I mentioned the specific pages previously.]

The specific approach (one of the several possible approaches recommended/ detailed in the document) is based on using the solder mask to control where the solder is allowed to flow.
The main objective being to avoid solder getting into the vias.
In particular, by creating islands of solder mask between the desired locations for the solder paste and having those islands of solder mask also covering the vias.

An excess of solder could cause the undesirable effects you mention.
However, for any of the approaches an excess of solder would generally have undesirable effects.

The solder could flow along the full bottom area of the ICs thermal pad whilst it would be somewhat discouraged from doing so as a result of having solder mask below it and also not being able to get into the vias
(since they are tented by the solder mask).

So an excess of solder could either
a) Flow under the full surface of the thermal pad metal of the IC (which is the same size as the thermal pad rectangle footprint).
b) Flow out the sides.
c) Lift the IC

I suppose the approach, by making it more difficult for solder to flow other than in the targeted solder paste areas, could increase the potential for the IC to lift in the event of there being an excess of solder paste.
Maybe (c) would predominate over (a) + (b)?
In which case, that would be a negative aspect of the approach.

However, for the approach you are thinking of, there could be alternative nasty effects.
Without an excess of solder paste, there is the potential for the solder paste to escape into the vias or even out of the sides leading to solder starvation.

In table 1 of Kelly’s document, it lists the pros and cons of each approach.
For “option 6 SMD windows” it claims the benefit of “Consistent standoff” amongst several other benefits.
Presumably that claim could be interpreted as: “for a consistent (correct!) amount of paste the standoff would be consistent since where the solder can and cannot flow is fairly tightly controlled”.

I am unclear as to what the relationship is in Kicad between the F.paste data and the stencil that will be produced.

People are telling me in this thread that the stencil will be produced using the F.paste data.

Looking at a UK-based specialist stencil manufacturer’s document, they make the understandable valid point that the paste drop that results from a stencil will be different from that of the physical aperture in the stencil.
No doubt the relationship will depend on many parameters including stencil thickness, type of solder paste, application technique, temperature, …

Is there anywhere in Kicad that we define a positive or negative offset to convert between F.paste data and the stencil apertures to be made?

Or, does the stencil manufacture adjust the provided F.paste data to make a stencil such that the paste deposits will more closely conform to the F.Paste target sizes?

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@Jonathan_Haas
Of course, I realise that green goo is not the inverse of solder paste in the material sense!
I was talking from the geometrical sense!

For a desired solder paste pattern, my understanding is that the green goo pattern is the geometrical inverse (subject only to a possible distinction between solder paste pattern and aperture sizes of the corresponding stencil).
I am talking about when the exposed copper (where the solder paste goes) is SMD-defined.
When N-SMD defined (‘copper defined’) the geometrical inverse does not apply since, by definition, the exposed copper is not related to the solder mask.

As I write above, I realise also that desired target for solder paste is related to but generally not the same as apertures in a stencil.

As for my reply to @paulvdh, I am doubtful that the statement “… for thermal pads, it’s definitely different”.
My understanding is that for “option 6 SMD windows” (Kelly report and NXP document to mention 2) they are closely related.

54

Yes, but only for that (relatively unusual) option.

55

First, I did not read your long response.

Simply put:
If you have a 0.2mm thick solder stencil, it deposits a 0.2mm thick solder paste layer. and this is too thick. Therefore normally the cutout of the solder stencil is smaller as the thermal pad. it can be as low as 30%. Result is that if the solder melts, it will form a layer of 0.06mm (neglecting flux content for simplicity) over the full area of the pad. This spreading of the solder is expected. With this small distance the pins are also pulled into the solder paste of the pads, and with so little paste the solder will not spread beyond the copper area of the thermal pad.
So your option “a” is both expected and recommended (but you start with only partially filled pads). Options “b” and “c” are bad.

Both are possible, and if both try to apply “corrections” then you get a mess.

56

This is not about KiCad at all, but about the (de facto) standard file formats and their de facto interpretations. Stencils are created exactly according to the gerber files (unless a reckless manufacturer thinks they know better and changes it without asking you), but the stencil holes aren’t cut directly vertically. However, the customer doesn’t care about that a bit, the manufacturer takes care about that. Just don’t spend your time on that any more. For all practical purposes, the Paste layer in KiCad defines the physical stencil. Period.

Even in Kelly’s “SMD windows” the paste graphics/stencil holes shouldn’t be the inverse of the mask, i.e. they shouldn’t cover all the bare copper. The reason was explained, and I think you understood the reason. Even in the Kelly et at. they show in real photos how the paste has been squeezed through holes smaller than the copper areas, and there are several paste blobs (holes in the stencil) for one copper area.

57

Aisler is apparently such a manufacturer (which quite surprised me)

Pad Shrinking
As we will take care of shrinking the SMD pads, the actual drawing should have no pad shrinking. Otherwise it’ll double. We shrink the pads by 15% in volume.

Source: Stencil Specifications - 📖 Design Rules & Specs - AISLER Creative Community

58

I think what you mean is that it’s possible to design the paste layer in KiCad so that paste areas are smaller than the land areas; and it’s possible for the manufacturer to adjust the paste layer if needed. But normally the manufacturer shouldn’t touch it without asking first. Maybe some manufacturers ask if each paste opening is identical to the copper land area, because they know that’s probably not what’s gonna work well.

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Surprises me, too, and I have to adjust my expectations. Actually I would appreciate such service if they take responsibility for it. Well, if a manufacturer does assembly, too, they know which works for normal pads. But it’s not simple with exposed pads which already have some shrinkage – or do they expect that the customer redesigns their thermal pads, and Aisler can guess how the customer thought the pads would behave? Or do they leave thermal pads untouched? What about (small) pads where the datasheet gives unusual recommendation for paste stencil?

60

I remind something that could bring some information into the discussion.
Someone manufacturing the stencil can’t modify the project he gets as he should assume that the right modifications were done before he got the file with project.
But someone who has the whole PCB project can apply offset to the F.Paste data as he knows how it should be done according to that PCB.
We order our PCBs at contract manufacturer. For me F.Paste offset was always 0 - openings at paste layer were the same as pad copper (I am speaking about standard pads, not thermal pads).
I assumed that stencil is just manufactured from Paste layer and never thought about it deeper. I was in such thinking until I used KiCad with rounded pads. Our contract manufacturer said that he has no tools to modify rounded rectangles in Paste so he can’t order stencil. To solve the problem fast I had to modify the Paste according to his instructions. It was the only once and about 4 years ago so I don’t remember details. Then he got the tool to do it himself and I could get back to my 0 offset.
The reason is not that you want to put less paste on pads but so that the stencil tightly adheres to the pads. Thanks to that paste (when it is spread over the stencil) not goes under stencil through gaps at the edges (you have to assume some random offset of stencil positioning).
I got from him a link to file to read those time, but that link not works now. Probably the following pdf is the same (I didn’t read it now):

Edit:
I see that during I was writing (it always takes me too long) the same topics raised.

61

@paulvdh If you have a 0.2mm thick solder stencil, it deposits a 0.2mm thick solder paste layer. and this is too thick.
Therefore normally the cutout of the solder stencil is smaller as the thermal pad. it can be as low as 30%.

As you state, the 0.2mm thick solder stencil is probably too thick - for example, that is the maximum thickness of the stencils offered by JLCPCB.
JLCPCB: “Standard thickness like 0.1mm, 0.12mm, 0.15mm, 0.18mm, 0.2mm are for free.”

So, rather than using a thickness of 0.2mm which is clearly identified as being “too thick”, why not use a more appropriate value for the example?
Your example seems to unfairly judge “option 6” by using parameters which are inherently not suitable for that option.

If you are talking about the area of the proposed solder paste in relation the overall thermal pad size in my example model, I would estimate it as being around 50% (based solely on a visual impression).

So, if a 0.12mm stencil were to be used for method 6 based on the 50%, a layer of 0.06mm would be formed over the full area of the pad, as in your example.

If flow type “a” is both expected and recommended, then are we not talking about a similar situation whether “option 6 SMD windows” or another methodology is being used

  • at least assuming that due consideration is made to specifying the most appropriate stencil thickness in association with the coverage ratio (whether 30%, 50% or whatever …) taking into consideration characteristics/ requirements of each method?

The argument could be turned around:
If you have a 0.1mm thick solder stencil, it deposits a 0.1mm thick solder paste layer and this is too thin.
For 30% coverage stencil, this would result in the deposit spreading to only 0.03mm thickness - even less since some solder would probably wick through the unprotected vias …
Associated bad things can be expected to happen …

It seems that a more reasonable summary may be that:
Each method has its relative pros and cons.
An appropriate combination of stencil thickness and coverage ratio must be used, reflecting specific aspects of each alternative methodology.