Thanks for your pdf.
This is another extensive document that relates to stencils from a UK-based specialist company.
I have only very briefly looked at it.
Remember that you donât order a stencil for a footprint, it is made for a board. If you calculate correct amount of paste for one footprint, you have to use the same stencil for all other footprints, too, and maybe adjust other stencil openings. Or you have to inform your manufacturer very precisely. Donât expect them to understand your reasoning, then.
Anyway, you have to follow the same logic for âSMD windowsâ than for normal copper defined exposed pads and all other pads. In the âwindowsâ the mask defines the area where the solder can flow when itâs melted. For normal copper defined pads the stencil opening coverage for that area should be tens of percents but not usually 100%. The SMD window is effectively a âlandâ for the solder because the solder canât go where there is mask. The paste shouldnât cover 100% of the land.
I have checked and it is not true.
He got the tool but I left right settings in all my PCBs. As I always start new PCB by copying my default PCB file I just donât need to remember some settings.
I have in all my projects Solder paste clearance set to -0.025. This is used only when paste is defined by copper. For thermal pad I add separate paste openings and they are not modified, I think.
If remember well it also happened that for one very small part I have set it to -0.02 (only for that part). Iâm not sure why, but there were some rules in the file I was reading (may be it is in the pdf I linked) saying when paste likes to stay on PCB and not went out with stencil and for very small pad using -0.025 violates those rules.
After that, my PCBs probably do not require modification of the paste layer, but if they did, it would probably be done without bothering me, so I wonât know.
Edit: At first I made a mistake rewriting the numbers - I entered too many zeros.
According to what I have heard from our contract manufacturer he always checks stencil regard pcb and modifies it. It is semi manual work. At typical PCB there are many the same sized openings (like all 0603 elements) that can be modified with one click. So someone is looking at each pcb carefully. If you left only pads and paste openings you will se that it is not so difficult to check if everything is correct (if you have practice and right working at gerbers program for it).
So I suppose if he would get PCB where only one element would be correctly modified he will modify the rest. And if he assume that this one element is wrongly modified than he will correct it also.
He is responsible for the assembled board, so itâs his task to make a suitable tool (stencil).
I am trying to move the ideas forward to realise a footprint in Kicad based on the Fusion 360 model.
I intend to implement two versions of the footprint, i.e., based on the somewhat novel âoption 6 SMD windowsâ (SMD defined approach) and the conventional approach.
By the end of this process I expect to at least have a good understanding of Kicad footprints!
For the âoption 6â, I have imported the Fusion 360 sketches into Kicad.
The thermal pad F.Cu has only F.Mask ticked, refer following graphic.
Bearing in mind that the mask is the negative of what is applied, means that, as desired, the starting point is that the full copper area of the thermal pad will be exposed.
[As I mention below, maybe I should change to first covering all the F.Cu with mask and then cut away âaperturesâ where the solder paste is to go?]
For the thermal pad B.Cu no mask is ticked so the corresponding bottom area of the PCB will be covered by mask.
However, the vias will be left open (i.e., untented) on the bottom of the board (following the property settings for the via pads).
I imported a dxf generated by Fusion into the F.Paste layer.
The result can be seen in the 3D view:
The challenge is how to convert the F.Paste outlines (lines and arc forming closed paths) into filled shapes that will result in paste being present everywhere within the shapes.
It is also necessary that the F.Mask has (what I have been referring to as) the âinverseâ of the paste shapes, such that solder mask covers all areas of the copper outwith the solder paste defined areas.
According to the approach (and guidance of AN2467.pdf), the mask should include all of the vias such that they become tented vias on the upper surface.
In summary, the visible upper surface of the thermal pad is desired to have solder paste within the shapes and solder mask everywhere else.
It seems that shapes can only be filled if they are first converted to pads?
So the solder paste shapes (currently drawn on F.Paste) need to be converted to pads? (How would that be done?!)
Or, should I instead first move the solder paste shapes to the F.Mask layer and convert those shapes to solder mask âpadsâ
It seems that I may need to go back and change to first covering the entire top surface of the pad with solder mask and then cut 'apertures" in that mask based on the shapes (converted to pads)?
That would result in there being solder mask everywhere exterior to the shapes.
Then, using the same shapes (that would have already been converted to pads in the previous step), use those âpadsâ to apply solder paste on the F.Paste layer.
I am not sure how to go about that since it seems that an (SMD) âpadâ must be associated with either or both F.Cu and B.Cu. In this application, the âpadâ only relates to solder paste!
It seems that only an âSMD apertureâ type pad need not involve the copper layers.
However, since I need to be, in effect, applying solder paste, the cutting effect of âaperturesâ is not what is wanted!
I should appreciate guidance as to the steps in the process.
Also how can the shapes be converted to filled pads?
I attach the footprint at its current stage:
SOT1172-3_ThermalVias_SMD.kicad_mod (44.4 KB)
Note that there is a different (standard Kicad) footprint at the bottom left.
That can be ignored.
I copied it into the overall footprint to facilitate comparison with a conventional example footprint.
@Douglas777 : First some words in advance (you could also skip the first paragraph and read only the tips) regarding the topic/your approach:
- First itâs good to try to understand the background of something. I appreciate also your work to search and read information.
- Nonetheless I think you make too much fuss about this topic. I think the difference between the proposed solutions is not relevant for most use-cases. Sticking with a simple, easy to design approach is good enough for >=95% of pcb-designers.
- important: all these discussion is theoretical. If you change the footprint (thermal-via count and -placement, position and size of paste, silkscreen on exposed pad yes/no) compared to a âoriginal kicadâ footprint you will only know after a real comparison (footprint in real use on pcb) if the new solution is better. You have to compare the resulting chip-temperature. Or use an X-ray research - this shows how good the soldering was and how big the soldered area really is (between chip-exposed-pad and pcb). Or you produce many (>1000?) units and observe the long-term-behaviour at customer-use.
- summary: you can invest much time/work into designing a complicated footprint, but you will most probably never know if it got you any advantage from that work. Itâs mostly guessing.
My rules of thumb for such footprints:
- maximizing the copper underneath the chip
- avoid one big paste-opening, instead use multiple paste-openings (see original NXP-picture)
- if possible: place the vias beside the exposed-padarea
- if possible: use a minimum of 6 vias on every side of the exposed pad. (more vias == better heat-treansmission to bottom copper. But this effect slows down with via-count >= 6)
- if vias are placed directly on the expased-pad soldering-area using your âsolder mask definedâ pad area works well.
- donât use geometrically complicated shapes (as your paste-shapes) - stick with simple rounded rectangle or circles
- these rules of thumb worked fine for all designs from the last >25 year (I hear them crying: the âwe have done it always this wayâ-argument). No soldering problems so far regarding the soldering of exposed pads (other problems occured).
- If some chip got to hot we didnât optimize the footprint soldering, instead: use a better chip / use more copper-area for cooling / improve the overall-cooling of the device
To give also helpful advice after these unrelated thinking:
The challenge is how to convert the F.Paste outlines (lines and arc forming closed paths) into filled shapes that will result in paste being present everywhere within the shapes.
The problem is that the dxf-import created the F.paste-items as lines/arcs. These canât be filled. You have to convert them to polygones. This involves a number of steps:
- select F.Paste layer in appaearnce-panel as active layer
- select dimming-mode so only paste-layer-items are selectable
- select the imported F.Paste-layer-item. There is a thin rectangle drawn around the items â all these items are grouped
- ungroup the selection (items still selected)
- RMB-clickâ>context-menuâ>Create from selectionâ> Create polygone from selection
- the original items are still selected. Hit âDeleteâ-key to delete the original items. (Alternatively move them out of the way)
- select one polygone after another, âEâ to edit polygon properties, select âfilledâ.
- if you are using the v6.99-version step 7) can be improved with using the âEdit Text&Graphics Propertiesâ-tool
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Actually I think this doesnât matter much. Even if the vias would be exposed, itâs the surrounding mask which prevents solder wicking.
Sometimes âvia tentingâ means not just the vias are covered as a byproduct of normal mask, but that an extra mask is applied on top of vias after the first layer of mask. Larger via diameter makes the normal first mask layer unreliable because the mask liquid flows into the via.
But this is really not something to worry about. Even if the vias arenât fully covered, the solder will stay out.
Remember that âviaâ normally means a through-hole which isnât a land area or for a component lead, and in KiCad âthermal viasâ are made as through hole pads. Just to make it clear because of confusing terminology, againâŚ
Hereâs again something to be confused about⌠What is âthe thermal pad B.Cuâ? And why âvias will be left open (i.e., untented) on the bottom of the boardâ?
To achieve what you want you should
- Have a copper pad for the component exposed pad, but all extra layers unticked.
- THT pads with all extra layers unticked for both top and bottom so that they work as tented vias.
- Separate custom shaped aperture pads in F.Paste for the paste stencil openings.
- Separate custom shaped aperture pads for the mask openings; their shape should be the same as the paste pad shapes.
- Finally, I repeat, the paste aperture pads should be smaller than the mask aperture pads, so that not all bare copper is covered by the stencil openings.
Question: (maybe somewhat off-topic)
What is an SMD aperture pad type in Kicad?
I searched the 'net but canât find an answer to this question!
The dictionary definition of âapertureâ is âan opening, hole, or gapâ (as, for example, a camera aperture that allows light to enter the camera).
For a test, using a rectangular pad and setting the pad type to âSMD apertureâ and having only F.Paste ticked, the result shows in 3D view as a rectangle of solder paste being deposited.
So how can this be understood as being an âapertureâ?!
Does it relate in some way to stencil apertures?
One or more layers can be ticked for the âSMD apertureâ pad type, whilst F.Cu and B.Cu are disabled.
So, what exactly is the meaning and potential usage of this âSMD apertureâ pad type?
On the subject of tented vias for thermal pads âŚ
@eelik: Actually I think this doesnât matter much. Even if the vias would be exposed, itâs the surrounding mask which prevents solder wicking.
Are you bearing in mind that the metal on the bottom of the IC package extends over the full area?
So, maybe the solder would tend to travel along the bottom of the IC and thereby get into the vias?
For this approach which isolates the vias from the solder paste areas, there seems no good reason to not cap (tent) the vias.
Even if it does nothing useful, I canât see that the tenting under these circumstances has any adverse impact.
@eelik: Hereâs again something to be confused about⌠What is âthe thermal pad B.Cuâ? And why âvias will be left open (i.e., untented) on the bottom of the boardâ?
By âthe thermal pad B.Cuâ, I meant the corresponding area to the actual F.Cu pad area on the bottom surface of the PCB.
It seems best to untent the vias at the bottom in case anything (solder, gases, chemicals or whatever âŚ) finds its way in, i.e., provide an easy escape route.
I shall now study âTo achieve what you want you should âŚâ
@eelik:
3. Separate custom shaped aperture pads in F.Paste for the paste stencil openings.
4. Separate custom shaped aperture pads for the mask openings; their shape should be the same as the paste pad shapes.
I think (based on a preliminary test) that it may be possible to combine steps 3 and 4 by using an âSMD aperture padâ which has both F.Paste and F.Mask ticked?
Or, does the following step 5 mean that is not possible?!
@eelik:
5. Finally, I repeat, the paste aperture pads should be smaller than the mask aperture pads, so that not all bare copper is covered by the stencil openings.
Yes, you have patiently mentioned this several times - but I still donât understand what actually needs to be done - or even what we are trying to achieve!
There appears to be two aspects:
a) The relationship between deposited solder paste and a stencil aperture.
As in previous comments, this depends on a number of factors including stencil thickness, solder paste type, temperature, âŚ
b) Whether we actually want the solder paste to cover a lesser area than that of the exposed copper (as it seems you are stating)?
The thickness of the stencil will influence the thickness of the deposited paste - so is it necessarily a bad thing for an appropriately thin layer of paste to be deposited on all the intentionally exposed copper area?
Is it not possible to use the âClearance Overrides and Settingsâ of the (SMD aperture type?!) Pad Properties to implement these (a and/ or b aspects) differences in size?
You need to talk to your assembly house.
They have the experience that you lack. They will know how their process works with large thermal pads - what percentage of the land pad that needs to be covered with solder paste.
If I were doing this, I would put an array of small vias under the pad, each one centered in the solder paste rectangle. They will tend to get filled with paste as it is screened, so they wonât steal solder from the pad, unlike vias that are placed in the alleys between solder paste rectangles.
At this stage my main objective is to achieve a good understanding of how to design relatively complex footprints based on particular design criteria.
i.e., to achieve an understanding of how to implement complex pad shapes, what exactly is meant by the âSMD aperture pad typeâ, how the Pad Properties function, âŚ
Such is generally useful knowledge for many other applications.
In this respect, whether or not the initial design criteria are good or bad is not of great relevance and is a distinct subject from how to implement details.
It is a separate subject as to whether or not the particular example I am working on is useful or over-complicated.
It simply serves as an example.
Regarding the thermal pad details, everybody seems to have different opinions - clearly that is a complex subject and application/ process dependent.
I followed the very clear list of steps provided by @mf_ibfeew for converting closed line/ arc paths to filled polygons.
I was pleasantly surprised how easy it was to covert the shape outlines to polygons following these steps!
As @eelik explains in his equally clear list of steps, it is then necessary to duplicate the polygons, with the duplicate being then re-assigned to the F.Mask layer.
The duplicated polygon serves to result in solder mask not being applied under the area (i.e., leaving exposed copper) whilst the original polygon serves to have paste on that same area.
Is there a way to copy and paste the polygons such that the copies remain in the exact same positions as the originals?
On doing the Ctrl-V, the copy seems to shift to a position related to the current grid.
I suppose I can use the smallest possible grid as a work-around.
Is there some sort of âPaste exactlyâ (i.e., in the position of the original that is being copied) facility?
I am aware of the âMove exactlyâ command but with the complicated geometry of the shapes I donât know what coordinate values to enter for such a move.
A polygon does not have any positional information in its Properties and it does not seem possible to examine any of the lines that comprise the outline of the polygon.
Before getting these instructions, I had assumed that the process would involve using SMD (or SMD-aperture) type âpadsâ associated with the shapes.
If that approach were possible (?) then the Pad Properties may allow clearances to be defined between the solder mask and solder paste?
The polygon objects (which are not âpadsâ) have no options in their properties apart from layer, line width and whether or not filled.
A polygon (even a filled one) does have the Property âline widthâ.
That raises the question as to whether the extent of the polygon shape is based on the centerline of the lines and arcs used to create it?
Or, does the polygon extend to the outer (or inner?) side of its defining lines and arcs?
Is there any way to select between these variants?
Changing the line width of a polygon to 0.0 visually shrinks the area of the polygon and appears to make the spacing consistent with the Fusion 360 model (which is based on the middle of line thicknesses).
@eelik keeps telling me that I need to leave some of the exposed (as a result of the polygons on F.Mask) copper without solder paste, i.e., have the polygons on F.Paste smaller.
A simple way to change the polygon sizes is to play with the line width; increasing that parameter increases the size.
However, negative line widths are treated the same as zero - so it only possible to increase the size, not decrease it.
Iâve also tried to explain why at least twice, but more likely 3 or 4 times.
Is there a way to copy and paste the polygons such that the copies remain in the exact same positions as the originals?
Yes.
First ensure in the general program settings: Preferencesâ>PCB-Editorâ>Editing Optionsâ> set Snap to Pads/tracks/graphics: set all to âalwaysâ.
Next set the grid to some coarse value. (1mm works mostly).
Now select and copy/paste a polygon. You will see a snapping-point at pasting-action so that the pasted polygon is exactly placed on top of the original.
That raises the question as to whether the extent of the polygon shape is based on the centerline of the lines and arcs used to create it?
Sometimes you should not only write long threads, but simply try and experiment yourself:
- draw a polygon on F.paste-layer. Set filled==yes.
- make 3 copies and place them to right of the original
- change line-width of these 3 polygones to 0.0001mm / 0.1mm / 2.0mm
- export as gerber and compare the result in the gerber-viewer.
spoiler:
the gerber-output shows: the line-width of polygones (and all other shapes) is taken into account at creating the output.
Exception: For the outline on edge.cuts the centerline of lines/shapes/polygones is used.
AN2467.pdf (page 22) explains this in a clear and more easily understandable way and also quantifies:
5.2.3 Stencil design
The dimension of the stencil openings should be a minimum 25 Îźm to 30 Îźm (5% to 10%) smaller than the size of the corresponding copper lands to account for alignment and PCB tolerances.
A fillet at the corners reduces the adhesion to the solder paste and improves the paste release (Figure 32).
I was confused by other explanations (from the many individuals) since aspects such as the relative coverage of solder in relation to the overall thermal pad area or thickness of the stencil muddled the subject (as least according to my interpretation/ understanding of what was being said at the time).
I appreciate your patience - most aspects are now reasonable clearly understood.
Page 23 also indicates that the minimum width of aperture for a stencil of thickness 150um is 225um - my pads at the corners are breaking that rule a little 
Remember that an exposed pad and its land area behaves differently than for example a 0603 resistor pad. For exposed pads the sources I have read talk about coverage in percentages for thermal pads, and so does your source an2467:
The stencil opening should be approximately 55 % â 70 % of the total PCB thermal pad area. This stencil-PCB thermal
pad ratio ensures proper coverage of the thermal pad area with fewer voids and minimizes the possibility of overflow
bridging to the adjacent lead
If you are trying to find an ideal coverage ratio for âSMD windowsâ I think youâre on your own, unless Kelly et al. tell it (I have read that document years ago, not now, and I donât remember if they do). It may be OK to cover more of the available copper than with normal paste aperture grid, but I donât think 100% is good.
We have already said that all this is mostly theoretical, you donât achieve any substantial benefit with this design. I understand well that reading and studying about this is beneficial, and you have learned and will learn much (we all would if we read the linked documents!), but IMO you should still use normal style footprints for real boards and keep âSMD windowsâ as an academic exercise.
This depends on the paste quality. The solder in the paste is actually small balls, there are different grains, and the larger the balls the larger stencil opening they require. Use larger minimum if you donât know which kind of paste will be used.
Even if you donât have expensive measurement devices (like X-ray) I think you could make an experiment. Create several footprints for the same part, order a PCB and a stencil and buy some paste. Find instructions for how to apply the paste through the stencil manually (there are for example youtube videos). You will see how it behaves. Set the part on the footprint. Even now you may see if thereâs too much paste. If you heat the PCB from the bottom side with a rework station or by other means, you can see what happens to the part when itâs soldered. This all would benefit you more than reading dozens of pages.
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