I tried to find a footprint for the NXP PCA9955B display driver IC which comes in an HTSSOP28 package.
I found a page on the NXP site which includes 3 versions for the PCA9745B (which I read is the same package as for the PCA9955B).
In theory, the .bxl files can be converted using the Ultra Librarian online tool.
I tried that process for each of the 3 versions but it reported an error message something like “no data found” when attempting to open any of the 3 .bxl files.
A question is therefore how could these bxl files be used; however, that question is not the main subject of this posting - I have plenty of other questions to discuss!
After much searching, I then found footprints from 2 different sources on the web but neither of them were accurately consistent with the NXP drawing in relation to dimensions.
These 2 other footprints were available in Kicad format but the dimensions were somewhat different from those in the datasheet and the thermal pad was only a simple rectangle (also inconsistent with the pad dimensions in the data sheet).
Maybe they are ‘good enough’ but, in any event, none of them included thermal vias in the pads.
This led to my investigating the subject of good practices in thermal vias and an attempt to define my own footprint.
The datasheet indicates that the package is also referred to as SOT1172-3 and an NXP file can be found for that (SOT1172-3.pdf).
SOT1172-3.pdf (727.1 KB)
The first question is:
What exactly is going on in the NXP drawing of the pad?!
It shows a rectangle encompassing 8 small rectangles.
As defined in the caption to the drawing, the darker shading is “solder land plus solder paste” whilst the remainder is “solder land”.
The question arises as to where would the thermal vias go in relation to those rectangles?
Also, why is there clearance between the solder paste and solder lands at the edges?
Also, why not use a single large area instead of 8 for the solder paste?
In attempt to answer my own questions, I have looked at an example in the Kicad library:
Illustrated as follows: (top Cu disabled so as to better see what is going on …)
It seems that the smaller rectangles (6 in this Kicad library example) define solder paste rounded rectangles, i.e., solder paste is apparently to be used in 6 pads rather than being spread over the entire pad area (as in the SOT1172-3.pdf drawing which involves 8 pads of solder paste)?
What is the rationale for doing it that way? What is the objection to using a single large deposit of the solder paste?
(Partly answering my own question?) Maybe the idea is that the vias can be positioned such that they are not fully covered by solder paste?
It seems to be generally considered as being undesirable to have solder enter the vias.
However, in this Kicad example, the holes of some of the vias (those in the corners of the pad) are fully covered by solder paste.
How do PCB manufacturers view this situation? Essentially, they are being asked to apply solder mask to an empty space (i.e., a hole).
The presence of the solder paste would clearly result in solder entering the vias - which according to my understanding is what we are trying to avoid!
As an aside/ another question/ issue arises as I am writing:
That is what is seen from:
View … 3D Viewer …
However, from within the footprint itself I am not seeing the solder paste in its 3D view (only copper is seen), refer:
Some time ago I recall disabling the solder paste somewhere in the viewing options.
Although this should be currently enabled in the View … 3D Viewer … Preferences … (since ‘Reset to Defaults’ was clicked),
the solder paste is not showing for the footprint (but shows when looked at from View … 3D Viewer …, i.e., the large 3D view)
Is this a bug? Or is there some way to separately define preferences for the particular footprint?
Returning to the main subject …
I found a document entitled “Via-in-pad design considerations for bottom terminated components on PCB assemblies”
The authors (Kelly, Jeanson and Ferrill of IBM) discuss 5 variants and propose a new variant “Option 6: SMD Windows”.
They provide some examples, refer:
I decided to try implementing the described approach based on the example shown in the bottom right of that graphic, which involves 8 vias, none of which are to be covered by solder paste.
I have used Fusion 360 - later I can export the drawing as a DXF and implement as a Kicad footprint.
Before I do that I should appreciate advice as to whether what I am doing seems reasonable and the specific details are correct.
The first question is what overall dimensions should be used for the thermal pad?
The drawing in SOT1172-3.pdf page 3 shows the suggested pad footprint as 3.4 x 2.2 mm.
On page 2 of that same document the physical size of the pad on the IC is defined as being 4.0 x 2.9 mm.
I am wondering why the pad could not be made larger (with the objective of providing more area for heat transfer) to at least the size of the physical pad on the bottom of the IC?
Is it beneficial for the pad footprint to be smaller that the physical pad to ensure that the component tends to float to the correct position during soldering as a result of surface tension?
But surely the 28 pins would control how the component may move during the soldering?
As seen in the NXP drawing, there is a 0.1 mm edge clearance between the thermal solder pads and the edge of the thermal pad and the same 0.1mm between each row of the pads.
At the left and right edges and between the columns the clearance is a little more, i.e., 0.12mm.
Kelly et al. show a similar clearance of undefined amount (i.e., note the green mask visible between the solder and thermal pad edges).
For the existing Kicad example (referred to previously), the edge clearances are less than 0.1mm and the clearance between rows and columns of the 6 pads are around 0.23mm.
[Since the Kicad example doesn’t have mask between the pads, why are 6 solder paste areas being used rather than a single large solder paste area?]
What is behind the thinking to not have the pads extend all the way to the edge of the thermal pad shape?
The clearance between the rows and columns is understandable for the Kelly et al. approach (as I am endeavouring to implement) since it enables mask to be between the rows and columns, with the benefit that the solder will tend not to get into the vias.
In my Fusion 360 model, I am using 0.2mm clearance.
JLCPCB capabilities web page states:
“Solder bridge. To have solder mask bridge, the spacing between copper pad edges must be 0.2mm or more.”
In my implementation, I have the mask extending as close as 0.05mm to the via hole perimeter.
If I understand the JLCPCB specifications, this relates to:
“Solder mask opening/ expansion. The solder mask should have a minimum of a 0.05mm ‘growth/ mask opening’ around the pad to allow for any mis-registration.”
So the green mask will not cover the hole in the event of the specified possible mis-registration - if my understanding is correct?
The result of my efforts is illustrated in a Fusion sketch and 2 views of the corresponding 3D model:
I have used blue for the mask rather than the more common green in the interests of clarity, i.e., to better distinguish from the PCB colour.
I could move the via centres closer to the edges to provide the benefit of larger solder paste areas - I shall probably do that …
This seems to achieve the objectives of the approach proposed by Kelly et al.
As I mention before, I have no spacing of the solder paste away from the perimeter of the thermal pad - perhaps I need to have that spacing?!
Thinking ahead to routing of the PCB using this component, it can be noted that pins 10, 19 and 24 are Vss which is the same as the thermal pad.
Pin 5 is nOE which will also be tied to Vss. One or more of the I2C address pins 2, 3 and 4 may also possibly be tied to Vss (depending on which address I choose).
So, it seems that at least pins 5, 10, 19 and 24 could be extended to join up with the thermal pad.
Of course, that would remove the possibility to route any tracks between them under the IC - probably I could cope with that since the intervening pins relates to connections to LEDs and I have freedom in how the LEDs are ordered.
I could create a special large version of the thermal pad footprint which involves also pins 5, 10, 19 and 24 as ‘wings’ to the pad (i.e, resulting in an H-shaped pad).
[Assuming that the oversized thermal pad doesn’t have any disadvantages - such as my above-mentioned concern that the IC may tend to float away during the soldering process …?!)
However, presumably a more reasonable approach would be to link the thermal pad to the pins during the PCB layout process when extra tracks and vias can be added?
In any event, if I use thick connections between the thermal pad and the pins I am, in effect, extending the size of the thermal pad.
Again, I wonder if that is desirable (since it would improve thermal dissipation) or undesirable (if bad things could happen such as the IC tending to float away during soldering …).
A final question relates to the dotted lines seen in SOT1172-3.pdf.
Presumably they are supposed to define a courtyard?
Yet the Hx dimension of 11.8 mm is very large in relation to the length of the IC (9.7 mm, dimension D on page 2)!