Thermal pad involving vias

I tried to find a footprint for the NXP PCA9955B display driver IC which comes in an HTSSOP28 package.

I found a page on the NXP site which includes 3 versions for the PCA9745B (which I read is the same package as for the PCA9955B).

In theory, the .bxl files can be converted using the Ultra Librarian online tool.
I tried that process for each of the 3 versions but it reported an error message something like “no data found” when attempting to open any of the 3 .bxl files.
A question is therefore how could these bxl files be used; however, that question is not the main subject of this posting - I have plenty of other questions to discuss!

After much searching, I then found footprints from 2 different sources on the web but neither of them were accurately consistent with the NXP drawing in relation to dimensions.
These 2 other footprints were available in Kicad format but the dimensions were somewhat different from those in the datasheet and the thermal pad was only a simple rectangle (also inconsistent with the pad dimensions in the data sheet).
Maybe they are ‘good enough’ but, in any event, none of them included thermal vias in the pads.
This led to my investigating the subject of good practices in thermal vias and an attempt to define my own footprint.

The datasheet indicates that the package is also referred to as SOT1172-3 and an NXP file can be found for that (SOT1172-3.pdf).
SOT1172-3.pdf (727.1 KB)

The first question is:
What exactly is going on in the NXP drawing of the pad?!
It shows a rectangle encompassing 8 small rectangles.
As defined in the caption to the drawing, the darker shading is “solder land plus solder paste” whilst the remainder is “solder land”.
The question arises as to where would the thermal vias go in relation to those rectangles?
Also, why is there clearance between the solder paste and solder lands at the edges?
Also, why not use a single large area instead of 8 for the solder paste?

In attempt to answer my own questions, I have looked at an example in the Kicad library:

Illustrated as follows: (top Cu disabled so as to better see what is going on …)

It seems that the smaller rectangles (6 in this Kicad library example) define solder paste rounded rectangles, i.e., solder paste is apparently to be used in 6 pads rather than being spread over the entire pad area (as in the SOT1172-3.pdf drawing which involves 8 pads of solder paste)?
What is the rationale for doing it that way? What is the objection to using a single large deposit of the solder paste?

(Partly answering my own question?) Maybe the idea is that the vias can be positioned such that they are not fully covered by solder paste?
It seems to be generally considered as being undesirable to have solder enter the vias.

However, in this Kicad example, the holes of some of the vias (those in the corners of the pad) are fully covered by solder paste.
How do PCB manufacturers view this situation? Essentially, they are being asked to apply solder mask to an empty space (i.e., a hole).
The presence of the solder paste would clearly result in solder entering the vias - which according to my understanding is what we are trying to avoid!


As an aside/ another question/ issue arises as I am writing:
That is what is seen from:
View … 3D Viewer …

However, from within the footprint itself I am not seeing the solder paste in its 3D view (only copper is seen), refer:

Some time ago I recall disabling the solder paste somewhere in the viewing options.
Although this should be currently enabled in the View … 3D Viewer … Preferences … (since ‘Reset to Defaults’ was clicked),
the solder paste is not showing for the footprint (but shows when looked at from View … 3D Viewer …, i.e., the large 3D view)
Is this a bug? Or is there some way to separately define preferences for the particular footprint?

Returning to the main subject …

I found a document entitled “Via-in-pad design considerations for bottom terminated components on PCB assemblies”

The authors (Kelly, Jeanson and Ferrill of IBM) discuss 5 variants and propose a new variant “Option 6: SMD Windows”.
They provide some examples, refer:

I decided to try implementing the described approach based on the example shown in the bottom right of that graphic, which involves 8 vias, none of which are to be covered by solder paste.

I have used Fusion 360 - later I can export the drawing as a DXF and implement as a Kicad footprint.
Before I do that I should appreciate advice as to whether what I am doing seems reasonable and the specific details are correct.

The first question is what overall dimensions should be used for the thermal pad?
The drawing in SOT1172-3.pdf page 3 shows the suggested pad footprint as 3.4 x 2.2 mm.
On page 2 of that same document the physical size of the pad on the IC is defined as being 4.0 x 2.9 mm.

I am wondering why the pad could not be made larger (with the objective of providing more area for heat transfer) to at least the size of the physical pad on the bottom of the IC?
Is it beneficial for the pad footprint to be smaller that the physical pad to ensure that the component tends to float to the correct position during soldering as a result of surface tension?
But surely the 28 pins would control how the component may move during the soldering?

As seen in the NXP drawing, there is a 0.1 mm edge clearance between the thermal solder pads and the edge of the thermal pad and the same 0.1mm between each row of the pads.
At the left and right edges and between the columns the clearance is a little more, i.e., 0.12mm.

Kelly et al. show a similar clearance of undefined amount (i.e., note the green mask visible between the solder and thermal pad edges).

For the existing Kicad example (referred to previously), the edge clearances are less than 0.1mm and the clearance between rows and columns of the 6 pads are around 0.23mm.
[Since the Kicad example doesn’t have mask between the pads, why are 6 solder paste areas being used rather than a single large solder paste area?]
What is behind the thinking to not have the pads extend all the way to the edge of the thermal pad shape?

The clearance between the rows and columns is understandable for the Kelly et al. approach (as I am endeavouring to implement) since it enables mask to be between the rows and columns, with the benefit that the solder will tend not to get into the vias.
In my Fusion 360 model, I am using 0.2mm clearance.
JLCPCB capabilities web page states:
“Solder bridge. To have solder mask bridge, the spacing between copper pad edges must be 0.2mm or more.”

In my implementation, I have the mask extending as close as 0.05mm to the via hole perimeter.
If I understand the JLCPCB specifications, this relates to:
“Solder mask opening/ expansion. The solder mask should have a minimum of a 0.05mm ‘growth/ mask opening’ around the pad to allow for any mis-registration.”
So the green mask will not cover the hole in the event of the specified possible mis-registration - if my understanding is correct?

The result of my efforts is illustrated in a Fusion sketch and 2 views of the corresponding 3D model:

I have used blue for the mask rather than the more common green in the interests of clarity, i.e., to better distinguish from the PCB colour.

I could move the via centres closer to the edges to provide the benefit of larger solder paste areas - I shall probably do that …

This seems to achieve the objectives of the approach proposed by Kelly et al.
As I mention before, I have no spacing of the solder paste away from the perimeter of the thermal pad - perhaps I need to have that spacing?!

Thinking ahead to routing of the PCB using this component, it can be noted that pins 10, 19 and 24 are Vss which is the same as the thermal pad.
Pin 5 is nOE which will also be tied to Vss. One or more of the I2C address pins 2, 3 and 4 may also possibly be tied to Vss (depending on which address I choose).
So, it seems that at least pins 5, 10, 19 and 24 could be extended to join up with the thermal pad.
Of course, that would remove the possibility to route any tracks between them under the IC - probably I could cope with that since the intervening pins relates to connections to LEDs and I have freedom in how the LEDs are ordered.

I could create a special large version of the thermal pad footprint which involves also pins 5, 10, 19 and 24 as ‘wings’ to the pad (i.e, resulting in an H-shaped pad).
[Assuming that the oversized thermal pad doesn’t have any disadvantages - such as my above-mentioned concern that the IC may tend to float away during the soldering process …?!)
However, presumably a more reasonable approach would be to link the thermal pad to the pins during the PCB layout process when extra tracks and vias can be added?
In any event, if I use thick connections between the thermal pad and the pins I am, in effect, extending the size of the thermal pad.
Again, I wonder if that is desirable (since it would improve thermal dissipation) or undesirable (if bad things could happen such as the IC tending to float away during soldering …).

A final question relates to the dotted lines seen in SOT1172-3.pdf.
Presumably they are supposed to define a courtyard?
Yet the Hx dimension of 11.8 mm is very large in relation to the length of the IC (9.7 mm, dimension D on page 2)!

Often the datasheets show only an example, a suggestion. They don’t give overly complicated instructions for paste layer. The paste stencil openings thermal vias are a branch of black science themselves. There’s no one optimal solution for all needs. You should know for example the used paste and the thickness of the stencil. Recommendations for optimal amount of paste (the area on the copper pads covered by paste in %) varies, it may be something like 60…80% which isn’t very accurate. Different components may behave differently.

The paste shouldn’t cover the whole copper area, there would be too much paste. One hole in the stencil (i.e. one paste area) shouldn’t be too large or it causes problems when paste is applied. You will notice that if you try to apply paste manually. The paste would go under the stencil because large openings let edges of stencil holes rise, and/or paste may not be applied evenly to the opening.

Actually I once sent gerbers with large paste openings to a cheap manufacturer, IIRC JLCPCB, and they modified the openings without asking. I didn’t like it of course, but after thinking for a while and learning more I understood why they wanted them that way.

It’s good to avoid paste on vias, but even that depends on the situation. The stencil openings in your Fusion design are overly complex. Maybe there’s nothing wrong with that, but it may be much work for little benefit. I would try to have proper coverage with simple shapes, avoiding vias but not being too pedantic.

It’s also good to remember the actual application for your component. What does the exposed pad and the vias do? They transfer heat away from the component. If the part doesn’t actually heat much in your application, you don’t need many vias. And you can add a larger zone – which itself transfers heat away – under the component and add more freestanding vias outside the exposed pad area.

I would try to be more practical, not perfectionist.

1 Like

Your post is much too long to read (and I did not read it all) but I did find a block with questions:

There are a few issues which are closely related.

If the solder paste cutout is the same size as the pad, then far too much solder paste will be deposited on that pad. The result is that the IC will float on a blob of solder and that the pins of the IC’s will not get soldered because they are too high above the pads. (Worst case scenario). When the solder melts it will spread out over the pad and form a thinner layer.

Solder paste is squeezed though the solder stencil openings with a squeegee, and this squeegee is flexible. This means that if there are big openings in the solder stencil, then the squeegee will partly dip into the opening and scoop up some of the solder paste. This results in less control over the amount of solder, and thus more variance in the sodering process. The ridges which divide the big pad into small pockets for the solder paste prevent this from happening.

These ridges also allow for air to escape from under the IC. An air bubble getting trapped wile soldering will prevent it from getting soldered properly.

The thermal vias are placed on the corners so there is no solder paste directly pushed into them during paste dispensing. This is again to better control the total amount of solder deposited on the pad.

A part of the solder will also wick into the thermal via’s. This improves the thermal conductivity of those thermal via’s.
Everything put together, it’s a bit of an art to get it right. If there is not enough solder on the center pad, then thermal conductivity goes down, but with too much solder, then the pins themselves may not get soldered, or all the excessive solder may disappear into the via’s and form drops on the other side of the PCB. Solder stencils are also not always the same thickness, which also results in different amounts of solder paste on the pads. I’m not sure though if there is a “standard” thickness for the solder stencil, and other thicknesses are on “special order”.

These air bubbles are also one of the two reasons to avoid paste inside vias. If the air inside the vias can’t escape (for example the other side is covered with mask, there may be an air pocket there which will be heated. The other reason is of course that the amount of paste varies if part of it sucked into vias.

Be careful with that. I haven’t seen component manufacturers recommending SMD windows. Also I’m not sure if you have understood and designed them correctly. The area which we see as blue in your Fusion screenshots must be drawn as EDA mask layer graphic shapes, not just be an area under the paste openings. I can’t be sure from the 3D representation if you have made it that way.

If I interpret your variant correctly, then you’ve made the cutout in the solder stencil the same as the cutout in the solder mask. This is probably not good, as the solder paste is likely to stay too thick in those area’s.

And as I mentioned before, solder wicking into the thermal via’s of the GND pad is not necessarily a bad thing. If you have such big protusions as posted in figure 10 on that website, then it’s an indication there is too much solder on the pad to begin with. If that solder could not escape into the via’s, then it’s likely the IC would have floated too high on the center solder blob.

There is some delicate balance, but I also agree with eelik that you’re probably overthinking it. That article seems to be written for high volume manufacturing, and trying to get a few percent (or less) improvement on yield and reducing rework. If you try to follow recommendations in that article without having the experience to know exactly what you’re doing, it’s quite likely you make your situation worse.

As a general comment, I believe that it is useful to clearly define the starting point of design criteria/ considerations which relate to such as thermal pads in footprints.
If my posting was considered as being over-long, please understand that my objective is an attempt to define a definitive guide to good practices on the subject, likely of general interest to others?

Only with such a clear definition is it possible to create new footprints (or understand the basis of existing footprints) based on some sort of logical process, rather than relaying solely on the subject of ‘black magic’ (i.e., what may or may not work based on ‘practical experience’ (of unknown others …), bearing in mind that such experience may be outwith the range of what that which has actually been experienced by a particular individual such as myself)! (In other words, based on my lack of practical experience relating to what works/ what doesn’t work, I tend to be rather cautious in my approaches …)

I agree in general with @eelik’s principle that:
“I would try to be more practical, not perfectionist.”

However, it is necessary to understand the various issues to be in a position to understand what is necessary and what could be practicable and reasonable simplifications.
In other words, what is actually practicable?! And when does an approach extend to become associated with perfectionism?! Without prior practical experience relating to ‘what works and what doesn’t’, one has no way of knowing!

For example, I remain unclear on (presumably important aspects) such as whether one could implement a thermal pad as a factor of (say) 2x larger than that shown in a datasheet.
Would the thermal performance improve or could the component likely float away from the intended position … (due to effects of surface tension, or whatever)?

@paulvdh wrote:
If I interpret your variant correctly, then you’ve made the cutout in the solder stencil the same as the cutout in the solder mask.
This is not good, as the solder paste is likely to stay too thick in those area’s.

I need to get my head around this …
I thought that the ‘solder stencil’ was determined based on the ‘solder mask’.
So are they not one and the same thing?
Where can one define a solder stencil in Kicad?

Solder mask (F.Mask and B.Mask layers) is the (usually green) stuff that covers the PCB in area’s where you do not want solder.

The solder stencil (usually a stainless steel sheet with a lot of holes for solder paste) are the F.Paste and B.Paste layers in KiCad. For a lot of smt pads these have the same shape, but not for the thermal pads. For SMT pads, you want a relatively large amount of solder, so it can “wet” the pins of the things that have to be soldered. For the thermal pads you only want a bit of solder under them, to prevent the IC’s from floating too high on a blob of solder, or from too much solder wicking into the pads and forming protrusions on the bottom, or even dripping off the PCB.

Also: I added the section below to my previous post while you were writing your response, so you may have missed it:

“Solder” is the tin, which for machine assembly is always paste. However, “solder mask” is a technical name for the substance which covers much of the board. Solder paste is applied through a stencil (high quality stencils are usually stainless steel). The paste layer in an EDA application describes holes in the stencil which is practically the same as the shape of the applied solder paste before heating (although the paste starts to spread immediately after applying). The mask layer is negative, the graphics in that EDA software layer describes holes in the applied mask substance.

The “SMD windows” technique above means that the green in their pictures is the mask substance in the board and it covers parts of the copper pad but not the whole pad, leaving uncovered areas. On those uncovered areas the solder paste is applied, and the solder paste stencil must have holes in those places. But the stencil openings and the applied paste aren’t exactly the shape of the grey areas in the image from Kelly et al. The grey area is probably the ideal (unrealistic) paste after it has been melt, for illustration purposes. But that grey area must be handled as a pad, i.e. some percentage of it must be covered by the paste. That is clearly seen in the real photos in that article.

Apologies, I realised that the ‘solder stencil’ is based on the F.Paste or B.Paste layers in KiCad, i.e., where the solder is to go, whilst the ‘solder mask’ defines where solder is not to go.
[It is very easy to get confused since the word ‘solder’ occurs in both ‘solder mask’ and ‘solder paste’!]
I believe that the Fusion 360 model is based on those principles.

Of course, the Fusion model does not/ can not define how the solder may melt and possibly flow elsewhere than intended!
The general thinking is that, as a result of the solder mask (blue) separations, the solder may be largely prevented from getting into the vias.
(Unless there is an excess of solder paste that can ‘jump across’ the mask separations.)
According to Kelly et al., that is generally beneficial, although as @paulvdh indicates it could be in one respect advantageous to have solder enter the vias thereby increasing thermal conductivity through the solder-filled vias.
If that is indeed intended, then one could define the footprint as for the cited Kicad example which has vias at the pad corners completely covered by solder paste.
Otherwise, the Kelly et al. approach offers the potential to better control where and where not the solder may go … albeit with the associated additional complexity of the footprint.

Of course. But you have drawn the paste exactly as the grey area in the Kelly et al. while it should be smaller. I would probably just do one exposed copper area as three separate rectangle shaped paste layer aperture pads with KiCad, although it depends on the size.

You seem to have the blue mask as one large rectangle. I don’t know what’s your plan here and how you have understood it and how this model should be understood. But finally each visible blue mask area should be a separate graphic shape in KiCad, it must not go under the paste layer graphics.

I have read that the paste tends to stay in the sharp corners of the openings in the paste stencil. If the corners are rounded paste stays on the PCB when stencil is picked up. A dirty stencil can lead to a shorts on the next PCB.

The starting parameter is what % of pad should be opened in solder stencil. And (if remember well) in different appnotes I found numbers from 25% to 80%. That depends on what is the height of thermal pad over PCB surface.
Imagine that IC pads (all other except thermal pad) are such that its thermal pad is at the same height that used solder stencil thickness. In such case I suppose 100% of pad should be covered with paste. If thermal pad is 0.1mm over PCB while stencil is 0.2mm (I don’t know what are the practically used thicknesses) then 50% of pad should be covered with paste. Really not 50% of pad, but 50% of not masked pad (pads can be ‘mask defined’ - opening in mask is smaller than pad itself).
The different % in appnotes of different IC vendors come from different IC construction and different assumption about stencil thickness (I have seen once the appnote saying this % for this stencil thickness and this % for this thickness).
So it looks that in theory for the same footprint but from different supplier you should use different %.
Till now I have used only few ICs with thermal pad. I am trying to be around 50% (as the middle value of what results from various sources).

I have no practical knowledge about soldering technology but have heard that if there are too much of solder at thermal pad then the surface tension on all pins will attract the IC to the PCB and thermal pad paste will spill out with risk of shorting other pins.

That also seems plausible, but either way, too much solder paste on the thermal pad is bad. Having excessive solder being sucked up by the via’s and protruding out the other side is probably the best of these 3 bad options.

The blue is solder mask which sits on top of the PCB copper but is only present where the solder paste is not to go.

The following illustrates the model with display of the (silvery-grey coloured) solder paste suppressed.
As seen, the blue solder mask consists of 5 elements sitting on the copper of the PCB.
It serves to restrict the ability of the solder to cross the mask and get into the via holes.

Does not “the grey area in the Kelly et al.” show where they are proposing paste to be?
So, yes I have the solder mask corresponding to Kelly’s grey area.
The only difference from Kelly is that my solder paste extends to the edges of the thermal pad.
As previously mentioned, I can suppress it by around 0.1 mm from all of the perimeter edges - that would make it look more like in the NXP datasheet and also as the example Kicad footprint.

1 Like

@Piotr wrote:

I have read that the paste tends to stay in the sharp corners of the openings in the paste stencil.
If the corners are rounded paste stays on the PCB when stencil is picked up.
A dirty stencil can lead to a shorts on the next PCB.

Yes, I can round the corners of the solder paste …
I can also use rounded rectangles for the 28 pads in Kicad.

I read on a web site that solder paste can typically range from 0.05mm – 0.15mm thickness.
My model uses 0.125mm which emphasises that the paste is much thicker than the solder mask (factor of 10x).

JLCPCB web site states:
Standard thickness of stencil like 0.1mm, 0.12mm, 0.15mm, 0.18mm, 0.2mm are for free.
The none-standard thickness will cost you: …

I don’t know what you mean by “If thermal pad is 0.1mm …”
Do you not mean “If solder mask is 0.1mm …”? Surely the thickness of the “thermal pad”, i.e., the copper is not relevant to coverage?
Since solder mask is much thinner than the paste then, in theory, an excess of paste may flow onto the mask and/ or into the vias (either that or the chip has to float up!). The other possibility is that the excess of paste would flow outside of the pad area.

Solder mask in the Fusion model is 0.0126 mm (JLCPCB state: Solder mask thickness 10-15um).
So the paste in the Fusion model is 10x thicker than the mask layer!

The bottom of the IC is slightly above the bottom of the 28 pads, refer data sheet.
A1 is 0.1mm nominal (ranging from 0.05 to 0.15mm).

So if a 0.2mm thick stencil is used with 50% of the thermal paste area being covered by solder paste, in theory either the IC would float up to be 0.2mm above the copper or the solder would flow over the solder mask (which it would be reluctant to do) or into the vias!

If a 0.12mm or 0.15 mm stencil was specified for JLCPCB whilst the solder paste covered 50% of the area then the IC should remain at around 0.1 mm above the copper whilst there would not be an excess of solder wanting to go anywhere?

I don’t understand what you mean by “pads can be ‘mask defined’”.
Is not the stencil aperture fully defined by the solder paste in Kicad F.paste?
Or is there a Kicad setting in which an offset can be specified?

It’s the same as “SMD windows”. Here SMD doesn’t stand for Surface Mount Device but Solder Mask Defined. The other option is Non-SMD which is a normal pad where the copper itself forms the land area. In a SMD pad the mask surrounds the land area and is partly on the copper, so the copper is larger than the land area. Interestingly, if you put for example a resistor footprint on a zone with solid connection or use very thick trace you accidentally form a pad which is a bit larger than a normal pad and which is Solder Mask Defined.

Where is ‘the same as “SMD windows”’ to be found in Kicad?

Is it Pad Properties … Pad type …?
In the Kicad footprint I mentioned, the solder paste pad is shown as being Pad type “SMD Aperture”.
“SMD” is another option in the Pad type drop down.

How does “SMD Aperture” differ from “SMD”?

Is the Kicad terminology “Surface Mount Device” or “Solder Mask Defined”?

It was only example value but important is longer text: “is 0.1mm over PCB”.
When you put IC on any flat surface it will be touching it with its pads. But its thermal pad is on some height over that surface and I was writing about that height.

No, in that place I was not considering mask in any way. Copper under thermal pad is at the same height as the copper under other pads but IC pads are touching copper but thermal pad is in some distance over it. At least I understand it that way. I just about 8 years ago had to use IC with thermal pad for the first time and read some appnotes and it is how I imagine it.

So exactly as I have assumed in: “If thermal pad is 0.1mm over PCB”.

No. You have to not understand something basic.
You have 100% thermal pad size.
You covered 50% of it with 0.2mm paste. So in average you covered thermal pad with 0.1mm of paste.
If distance between IC thermal pad and copper thermal pad is 0.1mm then everything matches and there is no too much paste to flow anywhere.

I added it only to not loose precision of my speech. To clarify that I am thinking about 50% of area of thermal pad (copper thermal pad) not covered by mask and not 50% of whole thermal pad (including parts covered by mask). Specially as you are trying to cover thermal pad partially by mask.
Copper pad can be smaller then opening in mask (not sure how it is named - copper defined pad), or opening in mask can be smaller then copper (mask defined pad).
Copper pad and opening in mask should not be the same. It is because of tolerances of placing mask at PCB. What would be the consequences if at one side mask will be partially on pad and on other side mask will start some distance from pad I don’t know. I just read that designing PCB you should clearly define pad by mask or by copper. I don’t know why sometimes in IC datasheet they write to use mask defined thermal pad (default for me is to have smaller pad then opening in mask).

Yes it is but it has nothing to mask.
When you get PCB from its manufacturer you can say this pad is ‘mask defined’ and this not (most are not). You need not to have stencil even manufactured to be able to say that so stencil has nothing to it.

KiCad doesn’t have any special property for that. The difference is only in the size of the mask opening compared to the copper pad. See How does solder mask layer work?. You can find more general information about NSMD vs. SMD by a simple internet search, for example “solder mask defined pads”.

Well, you mixed it up :slight_smile:

Excuse me, what? I don’t find anything which is mixed up.

As far as I know, every occurence of SMD in KiCad refers to Surface Mount. “SMD” isn’t used for Solder Mask Defined in KiCad. Having the same TLA in the industry to mean two different things which still are somehow related (both being used of pads) is of course very, very unfortunate.

“SMD Aperture” means a KiCad pad which doesn’t have copper but is in some other layer (and doesn’t have a through hole, therefore “surface mount”). Normal KiCad pads have copper and the possibility to choose some other layers. Normally both Mask and Paste are selected for a Surface Mount pad.

You should also get familiar with these Pad Properties:


And these board settings: