Based on a quick review of AN2467, my general impressions/ understanding are as follows:
Kelly et al.'s “Option 6: SMD Windows” seems to be the same as page 11 of AN2467 which states:
“The land array can be created either by segmentation of a full copper area by solder mask openings, …” (left illustration in figure 16).
Vias being placed as in the right hand illustration of figure 24, page 17.
My Fusion 360 model was based on this approach (although I didn’t as-yet define the edge of the overall thermal pad using a solder mask).
Of course, this is only one of many possible variants as covered by AN2467 and is not necessarily the ‘best’ (which would be application specific and influenced by production techniques - so there is no such thing as ‘the best’!).
At least this document validate’s Kelly’s approach as being of mainstream applicability rather than being only of academic interest.
It is only a little more complicated than any of the other approaches.
The main drawback of this “Option 6 …” may be that the solder mask needs to be at least 0.2mm wide (JLCPCB “solder bridge” specification).
In contrast, copper can be 0.127 or 0.09mm apart (JLCPCB “pad to pad clearance”) - that is the same as JLCPCB “Minimum trace width and spacing” for a 2-year board, whilst for a 4-6 layer board
the minimum spacing can be 0.09 mm. (The presence of via holes also needs to be considered since there are other specs to think about …)
So the solder paste area could be less than for other approaches - not necessarily a bad thing as long as the paste thickness is adequate.
Actually, on page 11, NXP state that “distance between lands should be 0.4mm”.
On pages 14 and 15 they show the distance as being 0.2 to 0.4mm.
An attractive feature of the “Option 6 …” is that the vias are located outwith the areas where the solder paste is applied.
If desired, the solder mask could be easily extended to provide tented vias, i.e., mask being over the vias.
Looking back at the Kicad library example I have been looking at:
VQFN-28-1EP_4x5mm_P0.5mm_EP2.55x3.55mm_ThermalVias
Interestingly, this Kicad example doesn’t seem to come within the coverage of any of the recommended alternatives in the 51-page NXP document!
AN2467 page 14: (alternative to the solder mask defined)
the exposed pad solder land can be split up into a pad array of single Cu pads as shown below in Figure 22 (the so-called copper-defined or NSMD approach, as in the caption to that figure).
In contrast, the Kicad example uses one large, non-segmented copper pad.
Only F.Paste and F.Mask are enabled in the following to make it easier to understand what is going on.
F.mask seems to be a single large rectangle of the thermal pad size.
Being the negative, that will result in the overall thermal pad sized copper of the PCB being fully exposed.
F.paste consists of 6 blobs of solder paste sitting on that continuous surface of copper.
Since the segments are not ‘copper-defined’ but only segmented in the sense of several solder blobs being deposited, there are differences in how the solder will flow (i.e., presumably in a less well defined way).
Gaps between multiple segmented small copper pads with bare PCB material between them would tend to keep the solder within the solder blob (stencil rounded rectangle) areas.
This aspect appears to make the associated question as to whether or not vias should be tented of increased relevance.
AN2467 page 17:
For copper defined array pad design option, it is recommended to place the thermal via in the center of the pad, as show in below Figure 25.
The via must be plugged, tented or plated.
Kicad is certainly not using SMD for the segmented pad and, as discussed, is neither using N-SMD (so-called ‘copper defined’) so it is generally undefined here in AN2467 where the Kicad vias should best be placed.
In the Kicad example, the vias are generally located outside of the solder paste blobs although the vias at the corners are located within the blobs.
The NXP ‘rule’ that the via must be plugged, tented or plated (at least for other than their SMD example) appears to be broken in the Kicad example.
Of course, it is easy and involves no cost to tent a via on its upper surface.
I don’t know if this is a typical example of a Kicad library footprint involving a thermal pad with vias or if I should be looking at a better example that is more consistent with, e.g., the NXP ‘rules’/ guidance?
A further question:
Is the stencil manufactured based exactly on F.Paste?
Are there any Kicad parameters that transform F.Paste to stencil definition (via offsets or whatever)?
Do PCB manufacturers such as JLCPCB themselves apply offsets to the F.Paste data in the process of producing a stencil?
" but in a very short form (in Polish: “I namieszałeś.”
