But the one I think I remember was the thermal pad - no tracks going out of it (other pads at all 4 sides).
May be in case of very small devices distance between thermal pad and other pads is so small that if you try to make thermal pad not mask defined then (assuming minimal mask offset and minimal mask width due to tolerances) you will get no mask between thermal pad and others what can lead to shorts. So the only possibility is to make that thermal pad mask defined.
AN2467 seems to provide a definitive guide to the subject, at least as recommended by NXP.
It benefits from clear graphics (unlike documents on the subject from other IC manufacturers).
I am busy studying the details from pages 7 to 17 in particular which seem to cover all the topics of this thread âŚ
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Based on a quick review of AN2467, my general impressions/ understanding are as follows:
Kelly et al.'s âOption 6: SMD Windowsâ seems to be the same as page 11 of AN2467 which states:
âThe land array can be created either by segmentation of a full copper area by solder mask openings, âŚâ (left illustration in figure 16).
Vias being placed as in the right hand illustration of figure 24, page 17.
My Fusion 360 model was based on this approach (although I didnât as-yet define the edge of the overall thermal pad using a solder mask).
Of course, this is only one of many possible variants as covered by AN2467 and is not necessarily the âbestâ (which would be application specific and influenced by production techniques - so there is no such thing as âthe bestâ!).
At least this document validateâs Kellyâs approach as being of mainstream applicability rather than being only of academic interest.
It is only a little more complicated than any of the other approaches.
The main drawback of this âOption 6 âŚâ may be that the solder mask needs to be at least 0.2mm wide (JLCPCB âsolder bridgeâ specification).
In contrast, copper can be 0.127 or 0.09mm apart (JLCPCB âpad to pad clearanceâ) - that is the same as JLCPCB âMinimum trace width and spacingâ for a 2-year board, whilst for a 4-6 layer board
the minimum spacing can be 0.09 mm. (The presence of via holes also needs to be considered since there are other specs to think about âŚ)
So the solder paste area could be less than for other approaches - not necessarily a bad thing as long as the paste thickness is adequate.
Actually, on page 11, NXP state that âdistance between lands should be 0.4mmâ.
On pages 14 and 15 they show the distance as being 0.2 to 0.4mm.
An attractive feature of the âOption 6 âŚâ is that the vias are located outwith the areas where the solder paste is applied.
If desired, the solder mask could be easily extended to provide tented vias, i.e., mask being over the vias.
Looking back at the Kicad library example I have been looking at:
VQFN-28-1EP_4x5mm_P0.5mm_EP2.55x3.55mm_ThermalVias
Interestingly, this Kicad example doesnât seem to come within the coverage of any of the recommended alternatives in the 51-page NXP document!
AN2467 page 14: (alternative to the solder mask defined)
the exposed pad solder land can be split up into a pad array of single Cu pads as shown below in Figure 22 (the so-called copper-defined or NSMD approach, as in the caption to that figure).
In contrast, the Kicad example uses one large, non-segmented copper pad.
Only F.Paste and F.Mask are enabled in the following to make it easier to understand what is going on.
F.mask seems to be a single large rectangle of the thermal pad size.
Being the negative, that will result in the overall thermal pad sized copper of the PCB being fully exposed.
F.paste consists of 6 blobs of solder paste sitting on that continuous surface of copper.
Since the segments are not âcopper-definedâ but only segmented in the sense of several solder blobs being deposited, there are differences in how the solder will flow (i.e., presumably in a less well defined way).
Gaps between multiple segmented small copper pads with bare PCB material between them would tend to keep the solder within the solder blob (stencil rounded rectangle) areas.
This aspect appears to make the associated question as to whether or not vias should be tented of increased relevance.
AN2467 page 17:
For copper defined array pad design option, it is recommended to place the thermal via in the center of the pad, as show in below Figure 25.
The via must be plugged, tented or plated.
Kicad is certainly not using SMD for the segmented pad and, as discussed, is neither using N-SMD (so-called âcopper definedâ) so it is generally undefined here in AN2467 where the Kicad vias should best be placed.
In the Kicad example, the vias are generally located outside of the solder paste blobs although the vias at the corners are located within the blobs.
The NXP âruleâ that the via must be plugged, tented or plated (at least for other than their SMD example) appears to be broken in the Kicad example.
Of course, it is easy and involves no cost to tent a via on its upper surface.
I donât know if this is a typical example of a Kicad library footprint involving a thermal pad with vias or if I should be looking at a better example that is more consistent with, e.g., the NXP ârulesâ/ guidance?
A further question:
Is the stencil manufactured based exactly on F.Paste?
Are there any Kicad parameters that transform F.Paste to stencil definition (via offsets or whatever)?
Do PCB manufacturers such as JLCPCB themselves apply offsets to the F.Paste data in the process of producing a stencil?
I have use unplugged vias in pads, but do go for a 0.3mm hole to reduce solder theft
There are different thoughts as to whether smaller or larger holes reduce âsolder theftâ.
Many (the majority of?) authors claim that a small hole is best (0.2mm is around the practical limit).
However, quoting from a report entitled: âThe impact of via and pad design on QFN assemblyâ:
Solder flow down to the via was seen for all the PTH via sizes tested in this study.
Solder protrusion onto the secondary size was seen for most of the via sizes with no solder mask ring.
The via with the diameter of 0.2mm (8mil) via with the actual hole size of ~ 0.10-0.13mm (4-5mil) hole didnât eliminate solder protrusion.
More solder protrusion was seen for smaller sized via.
On the other hand, 0.51mm (20mil) via with window pane stencil design resulted in no solder protrusion for 1.6mm and 2.4mm thick board.
â end_quote â
Of course, the subjects of âsolder protrusionâ from the bottom and âsolder theftâ are somewhat different.
Maybe the 0.51mm via is stealing a lot of solder as the via hole is being filled?!
The other consideration is thermal performance of the via.
Cheap manufacturers use thin plating for the vias.
JLCPCB donât seem to quote a spec. for this - they would need to be asked.
I read on the 'net that they may be using 18um - which corresponds to 0.5 oz copper.
So the amount of metal available to transfer heat is very small with a 0.2mm diameter via.
Increasing to 0.3 mm gives a 1.5x improvement.
My thought is therefore that, as you suggest, 0.3mm is a good diameter to use.
Larger diameters would consume area that could be used for solder paste, especially using the approach of isolation of the vias by solder mask as I have been talking about.
0.254mm hole and it still wicked and tilted 
This is one of those choices where the right answer depends on your assembly house.
My preferred PCB builder gets the power semiconductors nice and flat with no dry joints.
They make other mistakes, but not under this topic.
Filling vias would be an expensive requirement for me
One of my designs has four power FETs (500A) in TO-252 packages. I put an array of 15mil holes under the thermal tab, mostly for current sharing between top and bottom layers, but also for thermal performance. The vias get filled with solder paste when it is screened, and we have run many thousands of boards with no issues.
This is the Fusion 360 implementation of my latest thinking as what may possibly be the âbestâ thermal pad with vias?!
The silvery-grey is solder paste. This is sitting on top of a single large copper pad - so the principle is SMD (âsolder mask definedâ).
(Ignore the lines on top of the central row of solder paste - that is an artifact of the model resulting from using the Fusion mirror function.)
Everything else is solder mask (not shown in the model), i.e., the solder mask would cover all of the thermal tab apart from where the solder mask is seen.
[Update: correction to previous sentence:
That sentence should read:
Everything else is solder mask (not shown in the model), i.e., the solder mask would cover all of the thermal tab apart from where the solder paste is seen.]
The solder mask covers the edges of the thermal pad, gaps which define the solder paste edges and even the via holes.
So they are the so-called tented vias (covered by solder mask at the top but open at the bottom of the PCB).
The basis of the design is that the solder paste is spaced a defined distance from the via holes (0.25mm from the via centres, the vias being 0.3mm diameter) - the idea being to discourage solder getting into the holes.
As recommended in AN2467.pdf and most other sources, there is a defined spacing of the solder paste away from the perimeter of the pad.
Also, defined distances between the rows and columns of the solder paste blobs (the âlandsâ).
AN2467 states that "distance between the lands should be 0.40 mm.
I am breaking that rule in my model by using the smaller spacing of 0.2 mm.
Probably it is reasonable to do so since my approach includes a lot of space around the vias.
As I understand it, the purpose of segmenting the lands is to
(a) provide gaps for gasses to escape during the soldering process
(b) make the stencil work better compared to a stencil with a single large hole
(c) avoid solder paste being over a via hole position.
The next challenge is to transfer this to Kicad as a footprint ⌠!
???
Even this far down in this long thread you make the paste layer the same as the solder mask?
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Is a solder paste stencil with such narrow strips manufacturable and will it last in practical use, or will the squegee rip the thin segments when paste is applied?
That sentence should read:
Everything else is solder mask (not shown in the model), i.e., the solder mask would cover all of the thermal tab apart from where the solder paste is seen.
As I mentioned, the solder mask is not shown in this model. (It was shown in the Mk I although even in that model the mask wasnât shown at the perimeter of the thermal pad.)
My understanding is that the solder mask is the inverse of the solder paste.
In other words, where there isnât mask, solder paste will be deposited, as long as F.Paste defines the stencil (as people inform me it does).
Is there an aspect on which my understanding is mistaken?
Yes, there clearly is.
For normal SMT pad the solder mask is (approximately) the same as the solder paste. and when the solder melts it pulls the leg of the part towards the pad, and it also creeps upwards to form a fillet.
But this does not work for the thermal pad. The solder can not go upward, it also can not form a fillet. Therefore you part may float on a cushion of solder, and itâs pins may float above the pads without touching them, or when the pins connect to all the pads, the part may be pulled downwards hard enough that the solder gets squeezed out from under the IC, and both are bad.
The solution is to make the cutouts in the stencil smaller then the pad. This gives the solder room to go sideways when it melts and to form a much thinner layer. The result is that the IC is lower, so all the pins make contact with the solder on their pads, and also there is not enough solder to be squezed out from the thermal pad.
???
Again: Solder mask is the green stuff thatâs covering copper tracks and so on. Iâts neither the same as solder paste nor the inverse. The shape is often similar for SMT pads, put for thermal pads, itâs definitely different. You usually donât want to apply solder mask to the paste-free areas of a thermal pad. You want to have clear copper space where the solder can flow to.
@paulvdh But this does not work for the thermal pad.
Doesnât AN2467.pdf âAssembly guidelines for PwrQFN (Power Quad Flat no-Lead) packagesâ (51-page NXP recent document on the subject) detail that the approach I am working on is a valid approach?
[I mentioned the specific pages previously.]
The specific approach (one of the several possible approaches recommended/ detailed in the document) is based on using the solder mask to control where the solder is allowed to flow.
The main objective being to avoid solder getting into the vias.
In particular, by creating islands of solder mask between the desired locations for the solder paste and having those islands of solder mask also covering the vias.
An excess of solder could cause the undesirable effects you mention.
However, for any of the approaches an excess of solder would generally have undesirable effects.
The solder could flow along the full bottom area of the ICs thermal pad whilst it would be somewhat discouraged from doing so as a result of having solder mask below it and also not being able to get into the vias
(since they are tented by the solder mask).
So an excess of solder could either
a) Flow under the full surface of the thermal pad metal of the IC (which is the same size as the thermal pad rectangle footprint).
b) Flow out the sides.
c) Lift the IC
I suppose the approach, by making it more difficult for solder to flow other than in the targeted solder paste areas, could increase the potential for the IC to lift in the event of there being an excess of solder paste.
Maybe (c) would predominate over (a) + (b)?
In which case, that would be a negative aspect of the approach.
However, for the approach you are thinking of, there could be alternative nasty effects.
Without an excess of solder paste, there is the potential for the solder paste to escape into the vias or even out of the sides leading to solder starvation.
In table 1 of Kellyâs document, it lists the pros and cons of each approach.
For âoption 6 SMD windowsâ it claims the benefit of âConsistent standoffâ amongst several other benefits.
Presumably that claim could be interpreted as: âfor a consistent (correct!) amount of paste the standoff would be consistent since where the solder can and cannot flow is fairly tightly controlledâ.
I am unclear as to what the relationship is in Kicad between the F.paste data and the stencil that will be produced.
People are telling me in this thread that the stencil will be produced using the F.paste data.
Looking at a UK-based specialist stencil manufacturerâs document, they make the understandable valid point that the paste drop that results from a stencil will be different from that of the physical aperture in the stencil.
No doubt the relationship will depend on many parameters including stencil thickness, type of solder paste, application technique, temperature, âŚ
Is there anywhere in Kicad that we define a positive or negative offset to convert between F.paste data and the stencil apertures to be made?
Or, does the stencil manufacture adjust the provided F.paste data to make a stencil such that the paste deposits will more closely conform to the F.Paste target sizes?
@Jonathan_Haas
Of course, I realise that green goo is not the inverse of solder paste in the material sense!
I was talking from the geometrical sense!
For a desired solder paste pattern, my understanding is that the green goo pattern is the geometrical inverse (subject only to a possible distinction between solder paste pattern and aperture sizes of the corresponding stencil).
I am talking about when the exposed copper (where the solder paste goes) is SMD-defined.
When N-SMD defined (âcopper definedâ) the geometrical inverse does not apply since, by definition, the exposed copper is not related to the solder mask.
As I write above, I realise also that desired target for solder paste is related to but generally not the same as apertures in a stencil.
As for my reply to @paulvdh, I am doubtful that the statement â⌠for thermal pads, itâs definitely differentâ.
My understanding is that for âoption 6 SMD windowsâ (Kelly report and NXP document to mention 2) they are closely related.
Yes, but only for that (relatively unusual) option.
First, I did not read your long response.
Simply put:
If you have a 0.2mm thick solder stencil, it deposits a 0.2mm thick solder paste layer. and this is too thick. Therefore normally the cutout of the solder stencil is smaller as the thermal pad. it can be as low as 30%. Result is that if the solder melts, it will form a layer of 0.06mm (neglecting flux content for simplicity) over the full area of the pad. This spreading of the solder is expected. With this small distance the pins are also pulled into the solder paste of the pads, and with so little paste the solder will not spread beyond the copper area of the thermal pad.
So your option âaâ is both expected and recommended (but you start with only partially filled pads). Options âbâ and âcâ are bad.
Both are possible, and if both try to apply âcorrectionsâ then you get a mess.
This is not about KiCad at all, but about the (de facto) standard file formats and their de facto interpretations. Stencils are created exactly according to the gerber files (unless a reckless manufacturer thinks they know better and changes it without asking you), but the stencil holes arenât cut directly vertically. However, the customer doesnât care about that a bit, the manufacturer takes care about that. Just donât spend your time on that any more. For all practical purposes, the Paste layer in KiCad defines the physical stencil. Period.
Even in Kellyâs âSMD windowsâ the paste graphics/stencil holes shouldnât be the inverse of the mask, i.e. they shouldnât cover all the bare copper. The reason was explained, and I think you understood the reason. Even in the Kelly et at. they show in real photos how the paste has been squeezed through holes smaller than the copper areas, and there are several paste blobs (holes in the stencil) for one copper area.
Aisler is apparently such a manufacturer (which quite surprised me)
Pad Shrinking
As we will take care of shrinking the SMD pads, the actual drawing should have no pad shrinking. Otherwise itâll double. We shrink the pads by 15% in volume.
Source: Stencil Specifications - đ Design Rules & Specs - AISLER Creative Community