Post-V8 New Features and Development News

Solid 3D model export improvements:

  • Option to fuse copper geometry together
  • Option to export copper on inner layers
  • Options to exclude board body or components
  • Net filter (can be used to export a single net)
  • Zone geometry approximation with arcs for faster processing and smaller file sizes
  • Export in BREP or XAO formats

XAO defines pad surfaces as face groups and can be imported into SALOME or newer versions of Gmsh for FEM simulations:

28 Likes

Extended the physical_clearance rule to apply between copper fills & footprint courtyards.

(rule "No copper pours under Capacitors"
    (constraint physical_clearance (min 0.1mm))
    (condition "A.Type == 'Zone' && B.Reference == 'C*'")
)

will knock out the courtyard of any footprint whose reference starts with “C” from all copper fills.

10 Likes

@JamesJ added support for schematic rule areas that allow users to draw a shape to which net class directives can be attached.

38 Likes

small tool added (by S.Hillbrand) to the context menu: Shape modification–> simplify polygon

13 Likes

Control over via tenting on top and bottom sides, at a board level and per-via overrides.

Note: this replaces the “tent vias” checkbox in the Plot dialog, which is now gone.

21 Likes

Tables in Schematic Editor, Footprint Editor, and PCB Editor.

33 Likes

Mark items excluded from simulation:

12 Likes

DNP (and friends) at the sheet level:

25 Likes

@JeffYoung added a feature that lets you create ERC/DRC errors and warnings from textboxes and fields:

New text variables:

${ERC_WARNING <custom title>}
${ERC_ERROR <custom title>}
${DRC_WARNING <custom title>}
${DRC_ERROR <custom title>}

Variables must be at the start of a field, text item or textbox to be recognised by ERC/DRC.

They resolve to the empty string on the canvas.

18 Likes

Allow editing unit in Edit Reference Field dialog:

18 Likes

Plotting of pad outlines and numbers on fabrication layers:

14 Likes

Right-click action to remove Ignored Tests from the ERC/DRC dialogs:

21 Likes

You can now embed various elements in your schematics, pcb layouts, footprints and symbols:

  1. Worksheets

  2. Datasheets:

  3. 3d Models:

  4. Fonts:

35 Likes

Export silkscreen and soldermask as flat faces to STEP / GLB (Binary glTF) / BREP / XAO
(since May)

26 Likes

New ERC check for local and global labels with the same name (from Wishlist: ERC local/global net name collisions (#9461) · Issues · KiCad / KiCad Source Code / kicad · GitLab)

20 Likes

New ERC check for wires with unconnected endpoints.

24 Likes

Nets can now have multiple netclasses assigned. This can be used for fine-grained, modular, custom DRC rules. New functionality includes:

  • Introduces ordering of netclasses
  • Allows netclasses to have null properties (except on the default netclass)
  • Effective netclasses are constructed from non-null netclass fields in netclass priority order (with default netclass parameters always used as fallback)
  • DRC checks for netclass equivalence as requiring both items to have the same set of constituent netclasses
  • Modify DRC to test netclass name (A.netclass == ‘my_netclass’) against the comma-separated list of priority-ordered constituent netclasses
  • Adds DRC function A.hasNetclass(‘my_netclass’) to test if a given netclass is assigned to an item
  • Schematic and PCB netclass coloring taken from the effective aggregate netclass for a net

Note that we have also tidied up the case where previously the default netclass could have a schematic color assigned, but not a pcb color. Now, the default netclass can have neither color assigned. These should be set in the global color settings if customisation is required.

19 Likes

STEP export now supports exporting a subset of components based on what is selected in the PCB editor or a list of reference designators (supporting wildcards):

The latter is now supported in kicad-cli with the --component-filter option.

21 Likes

DRC skew rules now have an optional flag (within_diff_pairs). When set, the DRC rule is run independently for every identified differential pair in the traces which match the rule conditions. When left out, the current DRC behaviour remains whereby skew is run acros all matching nets (for example, for checking the skew of a bus). For example, for the following schematic:

With this board layout:

DRC with this rule:

(rule diff_skew
    (constraint skew (max 3mil) (within_diff_pairs))
    (condition "A.hasNetclass('DIFF_PAIR')"))

yields:

In addition, the router and DRC definition of skew have been unified to always be measured relative to the longest trace in the skew set (be that the longest in each diff pair, or the longest in all traces, depending on if (within_diff_pairs) is set).

The router will also pick up the correct constraint for skew tuning where skew is definied using a (within_diff_pairs) rule.

19 Likes

Layer pairs can be added to a preset list. “Enabled” pairs, along with the currently-set pair if not itself a preset, can be cycled with the “Shift+V” hotkey:


Pcbnew_layer_pair_cycle_dialog

17 Likes