I’m struggling to understand how clearances work in kicad.
If I assigned the net class of MAINS to my mains voltage tracks, with a clearance of 118thou then I would expect two tracks or pins assigned to that or any other net class to need a clearance of 118thou from anything else.
However, you need a clearance of 236thou. It’s no use changing the mains tracks to need a clearance of 59 because then the DRC looks for a clearance of 59+6 (where 6 is the clearance for low voltage tracks) and that’s too close to low voltage tracks.
So how do you do this please? There must, surely be a way to tackle this; in a thread of Christmas I was assured that kicad did this kind of thing really well these days, so I am sure I’m just missing something.
Also, is it really the case that you have to assign a netname to a track in the schematic to be able to assign it to a netclass? That totally gums up the schematic. For example, if you have a net connecting two pins of a mains transformer that is tiny on the schematic, it’s mental to have a net label on it. Or, indeed, one of those assign net class symbols. Is there really not a way round this?
Also, in v8, does it still need to be named in the schematic? (I’m assuming you’re talking about netclass assignment here and not how clearances work?!)
OK, so there is no way of doing it without having a named net or attaching one of those little symbols. Neither of which are what I want. Both of them make the schematic noisy.
If you could hide that little net class symbol it wouldn’t be so bad, but you don’t seem to be able to do that.
How exactly do you imagine adding a netclass to something without defining it some way?
Pattern matching. Best would be to google it. It is quite powerful, but honestly pretty annoying to write. I got good results with chat GPT writing regex for me
Well the nets are already defined as soon as you place them, so simply right clicking and assigning a previously defined net class would be best. Schematics should be clear and simple; having a net on a schematic that is, say, connecting the output of a mains filter to the input of the mains switch where that net is just a few millimetres long on the schematic gets really untidy when you place a net name or a net class assignment symbol.
That V9 system is no better, visible net class assignments don’t belong in a schematic. the schematic is there to help design the electronics and someone debug hardware issues, anything else is noise and distracting.
Thanks! That would be good were it in V7, it appears not to be. I guess I’ll just have to wait until my repository has V8 in it.
Fair enough, we see the schematic world in a different way then. My take is that someone coming along after the PCB is finished and is trying to debug the hardware does not want the distraction of net classes, it’s irrelevant to them.
