Pin not connected to fill

I have a pin that should be connected to the GND fill but it isn’t, how can I fix this?

The most obvious cause is that the zone is not set to the GND net. Each zone has a net name and only connects to pads of that net.

The pad (or the parent footprint) could also override the zone’s settings to say “no connection”.

(For 7.0 users, selecting the zone and the pad and then Inspect > Clearance Resolution will tell you why it is not connecting.)

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that pad properties are set as the should be.

@JeffYoung I am running v6.0 but I did run the clearance report.

Wild guess: Are there no other GND pads on the top copper layer? Asked as another question: How does the rest of the board look like?

@osterchrisi I counted 12 on the GND net and all connected to the fill but the one.

6.0 does not have the zone connection resolution info. 7.0 looks like this:

But for your issue it’s the “Clearance Overrides and Settings” tab of the Pad Properties that we need to see…

@TucsonDon : the pad-connection looks ok, the pad inherits the zone-connection-style “From parent footprint”. You now have to look at the same “clearance override” page of the footprint-parameter-dialog, if there is something unnormal. Normally there should be a setting that says: inherit pad connection: “use zone settings.”

My assumption regarding your non-connected pad is different:

  • THT-pads are normally connected with 45° thermal spokes.
  • above and below your unconnected pad nr.8 are horicontal tracks
  • so there is possibly no room for 45°-connection the pad, as that would create a clearance-conflict with the existing tracks
  • to test my assumption: delete one of the horicontal tracks and refill again

one remark: if you add your project as attachement (complete project-archive, not only the board-file) it is easier for all to spot the problem - we could directly investigate the problem instead of guesswork. Kicad contains so much parameters which all can influence such a behaviour. And it’s hard to write down all possible reasons for the behaviour (first in remember them and than regarding the time to write them down). (236.1 KB)

The zone is trying to connect with a thermal relief, but there is no room for a thermal relief. If you pull the +5V track above it a bit upward, or the track from Net-(J10-Pad1) a bit downward then there is enough room and KiCad creates the thermal reliefs.

Well… That was easy.

@paulvdh, Thanks for taking a look at it and your help!
@mf_ibfeew, @JeffYoung, @osterchrisi Thanks for your input and assistance!

It’s one of those many things you find quickly if you have the project itself and some experience. Without that you get guesswork and endles “try this, try that” conversations on the forum.

Also, You’ve stil got some work to do :slight_smile: In general, the routing of the PCB is pretty important. It is much more then just making connections. One of the main things of routing (a digital logic PCB) is the GND plane. Do a bit of research about GND planes, why they are important and how to make them properly.

I will, thanks for the input

Read articles I have mentioned some time ago:


Don’t you (all) think that KiCad should be clever enough to make in this situation horizontal thermal spoke?

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Don’t you (all) think that KiCad should be clever enough to make in this situation horizontal thermal spoke?

my opinion: No (only gut feeling). I fear inconsistency and an increased zone-filling-calculation time (zone filling is currently already a time-consuming step on my typical boards).

I admit that this could be a good feature, but that must be implemented as a “test/prototype” version and I fear (it’s fearing day): if something is implemented it will be not withdrawn if it doesn’t works as expected.

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Now add a ground plane on your bottom layer as well. Then add stitching vias to really tighten up the ground system. When you add a ground stitch via in those areas on top where there is no plane – boom, you have top plane…
Maybe fatten up those traces. They look pretty weeny going into those big thuhole pads and solder heating can sometimes cause a crack… Or give them a fattening transition with two trace sizes:

Don’t throw in too much at once. A single good groundplane is preferable to a stitched together quilt. And concering that crack prevention, KiCad V7 (Expected soon) is going to get built in support for teardrops.

Yeah teardrops will be nice.

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