How to tent in-pad vias? (for thermal pads)

I am working with an 8-pin HSOIC that has a thermal pad. The manufacturer (TI) recommends tenting the thermal vias in the thermal pad to reduce solder loss:

“As an alternative, if the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias on the component side with a dimension equal to the via diameter + 0.1 mm minimum.”

I can’t find an easy way to do this in Kicad 6.0.9. It requires cutting holes in the pad’s solder mask - and Kicad doesn’t allow the creation of islands (holes) in solder mask shapes, so far as I can tell?

Not directly. But you could probably remove the solder mask layer from your thermal pad and then draw the solder mask free area separately on the solder mask layer using a rectangle with hole cutouts. (Probably draw a rectangle and multiple circles and combine them to one shape using the context menu. Or import that shape from a vector or cad program if you want)

I am puzzled how deliberately keeping the mask away from the via will block the via.
My experience is that 0.3 mm vias don’t rob too much solder

The soldermask layer is inverted (mask is put where the layer isn’t), so the idea is to tent the via, not keep the mask away from it.
Yes, I’m thinking 0.3mm untented might be OK, but it isn’t what TI recommend.

OK, so they are placing resist just over the via hole + a minimum annular wing of 0.1 mm

Using a minimum via size seems to work, epoxy fill raises costs quite a bit.

Yes, epoxy fill would be best avoided. Simply tenting the via with soldermask is essentially free, but seems can’t be easily designed in Kicad.

it could be done with a macro/plugin to create resist circles only on defined vias, then this should be subtracted to solder mask … not a fast task.
I don’t know if it is possible to add keepout circles for mask layer…

A thermal pad normally doesn’t have solder mask at all, so I’m a bit confused by the premise of the question.

KiCad today tents vias by default in the Gerber plotter. KiCad will not add solder mask on top of a copper pad, though, so for vias-in-pad this has the effect of tenting the side of the via opposite the thermal pad (which is generally what you are after, I think)

IPC-7093 captures the notion of Solder Mask Defined Thermal Pad so I wonder if this is what the OP is referring to. If they were to make an appropriate footprint pattern then the “tented via’” option would do (although selective tenting might be best)

product says hi: Include heatsinking vias of footprint to GND area - #6 by Naib

0.3mm is a bit big, I don’t see issues with 0.2mm in most cases though.

Currently KiCad doesn’t really support selective tenting, unfortunately.

That particular design was 0.24mm ( Include heatsinking vias of footprint to GND area - #13 by Naib) - tenting was accidently forgotten. Just pointing out its a real issue and sure smaller should mitigate it but sometimes you can’t go smaller due to aspect ratio and thus being mindful of wicking is always wise and then you can make an informed decision.

Even if kicad could, the issue would be how to present the need to the fabricator. The only method I use for selective-tenting or filled via’s is a specific via size (even if it is a silly decimal-place difference) and inform the fab “all vias of 0.240001 are to be filled” OR a selective region as part of a drawing pack

Along with the exactly same issue with many other technologies. There’s no any standard way to communicate that to manufacturers. I think it’s usually a note “all vias in pads are filled/tented in this or that way”.

On the other hand the situation in general is somewhat understandable because we can’t know if someone invents, say, two new techniques for tenting vias tomorrow, fullfilling a bit different needs so that both would be used in one board. Supporting “these vias are tented” wouldn’t be enough anymore. Considering how even old standard gerber features aren’t supported by many manufacturers, it would be too much to assume that they could follow new standard features even on yearly basis.

I wish the manufacturers could at least agree on some new standard layers, like “Solder Mask Defined pads” which would mark those SMD pads which some manufacturers now require communicated in non-standard text form “pads of U10 are Solder Mask defined”. It would be so much easier to mark pads as Solder Mask Defined in the footprint and then let the plotter plot SMD gerber layer which would automatically show them to the manufacturer.

1 Like

I looked at keepouts - the soldermask layer isn’t an option.

Not in this case - the mask is on the component side, preventing solder from entering the hole.

0.2mm costs more

Some fabricators cost more, for holes smaller than 0.3mm (PCBway does, for example). While resist is free.

Easiest to just have it defined in the mask layer gerber, then there is no need for notes to the fabricator?

Tented vias can be defined in the mask gerber (but KiCad can only tent or un-tent all vias, not individual ones at the moment). filled vias (which generally means epoxy fill) must be communicated by special notes.

Are you sure? I’ve never heard of selectively applying solder mask to the component side of a via-in-pad, it seems to me that it would be a risky process as it might interfere with the component seating to its footprint. I have only seen solder mask applied to the other side of the via (where no part is soldered) which works fine for some situations.

In situations where solder mask on the opposite side (and using a suitably small via drill) are insufficient, the only thing I’ve seen done is filling and capping the vias (with epoxy and metal, not with solder mask)

1 Like

It’s right there in his first post.

Discussion here: