I was under the impression that wicking meant that the via sucked the solder away from the pad (inside of the via or to the other side) and therefore there was not enough paste in the pad for the components, but am I understanding correctly that the via “bump” the MCU up, due to the solder inside of it ?
You are totally right and that’s exactly what happened. One side of this uModule had a "ground zone For thermal reasons and uncapped vias. The other side had control (feedback, uvlo, as etc). During reflow the ground zone, via the … Vias … Wicked the solder causing the entire part to tilt as one side was dragged closer to the PCB due to reduced solder and surface tension.
Does “via in pad” mean one thing? Of course… putting vias in pads from the fabricators perspective it means filling via’s and leveling vias due to them being place on a pad. This is why I made a distinction about “via in pad” (from the perspective of layout) and “via in pad” (from the perspective of fabrication and assembly) because while they are related they have totally different ramifications and influence other aspects of the design as well as what additional information needs to be provided as this can wreck cards if you are not careful or drive unneeded cost if you are not aware
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Hi all, thanks for the tips so far. My Kicad version i am using is 5.1.9 and the footprint is of step down dc-dc converter TPS54332. The technical datasheet is available here: https://www.ti.com/product/TPS54332. I now how to set vias and create them, but what i am wondering how i can set the vias to the ground area. I will attach pictures for description. On page 25 of the dataseheet is it described how to do it and here is my pcb bottom side so far:
The eeschema symbol should have a TAB or THERMAL pin you can tie to GND.
Yep.
If your schematic symbol is lacking a pin for the tab, then first look up the pin “number” in the footprint (which can be any four character alphanumeric string) and add it yourself to the schematic symbol and tie it to the appropriate net (GND).
What was the diameter of those vias?
I have read somewhere that to avoid wicking via hole diameter has to be smaller than 0.3mm.
In rare cases when I have thermal pad I add 0.3mm holes (and consider if not to change them into 0.2mm). I really don’t need power dissipation close to case limits so even the end effect would be my thermal pads not soldered I would probably not notice it. So the only I can say is - I didn’t noticed any problems with it.
I just opened the GERBER’s and the drill table has these at 0.254mm.
So, what I have read seems being not true 
I supposed that so small holes are just covered by solder-mask at bottom and because of being closed on opposite side had no potential to wicking the tin.
But I have really no experience with soldering technology.
I didn’t tried doing 0,2mm holes as they looked for me as being too small to be done
Well that’s the thing about rules of thumb, there is always some small print about when it is applicable and when it is not.
I am on-site today so I have taken a picture of the backside . In total this design used 5 uModules as PoL (1v2, 3v3, P15, M15, 5V ) just to evaluate, especially as they are a waste for a couple of rails
You can see that it’s wicked through some of the vias, enough to cause a collapse
What is the reasonable reason to not cover vias by solder-mask?
I have read conflicting information about if it is a good idea to cover vias on only one side (application notes of different manufacturers disagree with each other here. So do suggestions by fabs but the latter seem to try and sell you a more expensive option so not sure what to make of that).
Generally there is the argument that this would allow contaminants to be trappend between the solder and the closed end of the via which could lead to voids. Others seem to indicate that this is less of an issue than the potential to loose solder through wicking.
So my personal guess is that there are too many variables at play so i would assume the answer possible is “it depends but we do not know on which other variables”.
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Another argument I’ve heard is that when via’s are tented on both side they trap a bit of gass, and apparently this can get released violently enough during heating in the soldering process to cause problems.
I do not have a SMT production soldering strait so I can only parrot what I’ve read somewhere else.
I Do have noticed that sometimes with the plated through matrix boards the solder is “bubling” quite a lot from gasses coming out of the PCB.
Hi, what do you mean with this TAB or THERMAL pin. In my footprint editor it looks like this.
Shall i change the pad connection from “from parent footprint” to “thermal relief” for all 8 vias?
If you want to use a pad as a heatsink, then never use thermal reliefs, as they defeat the purpose of heatsinking.
The diameter of your via’s also look very small. Drilling becomes more difficult (and therefore possibly extra costs for you) when the diameter becomes smaller as about 3x the thickness, so for a standard 1.6mm PCB that would be a minimum hole diameter of 0.5mm (finished hole, the drilled hole would then be a bit bigger)
I also see that your via’s have pin number “10” while the pad has pad number “9”. That does not work. Give them all the same pin number.
If that footprint at PCB has not set its connection to Solid, or zone has not it set to Solid than you should set ‘Solid’ for all 8 vias and for thermal pads, I think.
Thermal pad is the metal at bottom of IC. Its purpose is to allow for heat transmission from internal IC structure to PCB.
Thank you all. Finally i get it working. I changed the footprint with a different one which has a thermal pad included and routed that to gnd and it works.
Meh, you’re taking shortcuts.
If you want to understand KiCad better, then compare the differences and learn from why your own footprint does not work properly.
It’s probably something simple such as the diffence between pad Nr 9 and pin numbers “10” for the via’s.
In this instance… Forgetting to indicate which vias need to be tented to the fabricator - it would have only been one side
The usual reason I am given not to tent both sides is the pocket of air that can pop under reflow
I have only once (several years ago) heard about that problem and now I realized - I have completely forgotten it. Our contract manufacturer never complained on it.
Looking closer to one my assembled PCB I think I know why. I use 0.7 and 0.5mm vias end even they are nominally covered by solder-mask they are really opened - too big to be closed with solder mask. At that PCB I have six 0.3mm vias at one thermal pad so one side is not covered, and I see that second is not plugged by mask (also too big to pe plugged) so you can expect wicking.
I don’t have a microscope, but using lamp with magnifying glass + hand magnifier I don’t see tin at least half way deep (1.5mm PCB).
May be the wicking problem was bigger with Pb soldering. I think PbFree solder has lower wetting capability.
Thanks. I hope I will not forgot once more about that problem, but fortunately I can don’t care of it now
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