Include heatsinking vias of footprint to GND area

Hi, i am new to KiCAD and designed a pcb for reducing 24V to 5,1V. Everything works very well so far. I have 1 last problem with a footprint of Texas instruments. This voltage regulator have 8 vias under the ic which should be connected to the gnd area. There is a recommendation in the technical data sheet, but i am not able to include these vias to my gnd area. Any suggestions how to do it would be highly appreciated. Thx.

Welcome ! Glad to hear that you are having fun with KiCAD !

Which footprint is that, could you write the full name and maybe link to the technical documentation?

Why are you unable to do it? Do you not know how to create vias? Are the vias too big ? Pleases do explain a bit further in able to do any kind of suggestions.

it is always helpful to state exactly which version of KiCAD you are using, there are some well know bug with some old version or different ways to achieve what you wish.

Open KiCad Footprint Editor and look how it is done in KiCad Library.
In Library Package_DFN_QFN each footprint with name ended with “_ThermalVias” contains that.
For example:

In KiCad Library you probably will be able to find the right footprint for your IC.

as @Piotr has shown, there are relevant footprints with thermal pad GND via’s.
However… do you really want to go this way? Technically this is “Via in Pad” and this results in one of two things

  1. Via’s are placed just like this and during reflow the solder wicks through the via’s and can cause issues

  2. You formally request “Via-in-Pad” from your fab house and they epoxy fill these vias to mitigate wicking. This is an additional cost.

In either case putting via’s in a pad will drive additional process at the fab to ensure the pad is level post-drilling. This drives cost or some fab’s don’t care.

One option is to question whether you need it and extend the pad outside of the part and via to GND outside the courtyard. This is obviously not an option for QFN’s but sometimes there is enough GND pins to permit this as well.

No it’s not.
“Via-in-Pad” is a standardized term in which the via’s are filled to prevent the wicking, as you write in your option 2).
Just placing via’s in pads does not make it “Via-in-Pad”.

Thermal via’s are quite common, and I’ve never seen them as “Via-in-Pad”. The epoxy, or whatever they use to fill the via’s (They can even be copper plated over the filling (Yes, that’s expensive).

“Via-in-Pad” may be necessary for BGA’s where there is not enough room to place via’s in between the balls. With those BGA’s the amount of available solder is quite limited, and also the same for each ball.

With these big thermal pads however, there is plenty of solder to solder the pad to the GND plane. The wicking is also not a problem. The gap between the pad on the IC package and the PCB is narrower then the via diameter, so it has a stronger wicking action than the via’s. Just the excess solder will wick into the via’s, and improve thermal conductivity. If the design of the footprint is good, then the aperture size for the stencil is also adjusted to get the right amount of solder on the thermal pad. Many of the “ThermalVias” Footprints in KiCad’s have “aperture pads”. These aperture pads do not exist on a copper layer and do not have a pad number.

With a BGA it’s completely different. The balls have a strong surface tension, and try to keep sort of round, and this creates a gap between the BGA and the PCB. If some of the pads then have a via under them, the solder gets wicked away, and those pads may get starved of solder.

Well… when it comes to the design there is only one type… putting a via in a pad.
When it comes to the fabrication this is where the distinction comes as you may or may not want/need to fill said vias. The reason I am stressing the distinction is no eCAD tool nor fabrication format (GERBER,ODB++) contains information as to whether you want to fill the via’s and which one or with what epoxy. such information is part of the fabrication datapack

Also, I disagree that with big thermals pads that there is plenty of solder and thus the wicking isn’t a problem. I have a design from 2 years ago where I did not request tenting via’s and a uModule lifted due to the wicking…

extracted one of the images from my MantisBT setup.

One out of the 5 cards hard open-circuit due to the tilt. 2 had good connections and two had “suspect”, all determined via xray

tl;dr it isn’t a problem to just be dismissed and it is always advisable that people are aware of the ramifications so they can make an informed decisions

I was under the impression that wicking meant that the via sucked the solder away from the pad (inside of the via or to the other side) and therefore there was not enough paste in the pad for the components, but am I understanding correctly that the via “bump” the MCU up, due to the solder inside of it ?

You are totally right and that’s exactly what happened. One side of this uModule had a "ground zone For thermal reasons and uncapped vias. The other side had control (feedback, uvlo, as etc). During reflow the ground zone, via the … Vias … Wicked the solder causing the entire part to tilt as one side was dragged closer to the PCB due to reduced solder and surface tension.

Does “via in pad” mean one thing? Of course… putting vias in pads from the fabricators perspective it means filling via’s and leveling vias due to them being place on a pad. This is why I made a distinction about “via in pad” (from the perspective of layout) and “via in pad” (from the perspective of fabrication and assembly) because while they are related they have totally different ramifications and influence other aspects of the design as well as what additional information needs to be provided as this can wreck cards if you are not careful or drive unneeded cost if you are not aware

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Hi all, thanks for the tips so far. My Kicad version i am using is 5.1.9 and the footprint is of step down dc-dc converter TPS54332. The technical datasheet is available here: I now how to set vias and create them, but what i am wondering how i can set the vias to the ground area. I will attach pictures for description. On page 25 of the dataseheet is it described how to do it and here is my pcb bottom side so far:

The eeschema symbol should have a TAB or THERMAL pin you can tie to GND.


If your schematic symbol is lacking a pin for the tab, then first look up the pin “number” in the footprint (which can be any four character alphanumeric string) and add it yourself to the schematic symbol and tie it to the appropriate net (GND).

What was the diameter of those vias?
I have read somewhere that to avoid wicking via hole diameter has to be smaller than 0.3mm.

In rare cases when I have thermal pad I add 0.3mm holes (and consider if not to change them into 0.2mm). I really don’t need power dissipation close to case limits so even the end effect would be my thermal pads not soldered I would probably not notice it. So the only I can say is - I didn’t noticed any problems with it.

I just opened the GERBER’s and the drill table has these at 0.254mm.

So, what I have read seems being not true :slight_smile:
I supposed that so small holes are just covered by solder-mask at bottom and because of being closed on opposite side had no potential to wicking the tin.
But I have really no experience with soldering technology.
I didn’t tried doing 0,2mm holes as they looked for me as being too small to be done :slight_smile:

Well that’s the thing about rules of thumb, there is always some small print about when it is applicable and when it is not.

I am on-site today so I have taken a picture of the backside . In total this design used 5 uModules as PoL (1v2, 3v3, P15, M15, 5V ) just to evaluate, especially as they are a waste for a couple of rails

You can see that it’s wicked through some of the vias, enough to cause a collapse

What is the reasonable reason to not cover vias by solder-mask?

I have read conflicting information about if it is a good idea to cover vias on only one side (application notes of different manufacturers disagree with each other here. So do suggestions by fabs but the latter seem to try and sell you a more expensive option so not sure what to make of that).

Generally there is the argument that this would allow contaminants to be trappend between the solder and the closed end of the via which could lead to voids. Others seem to indicate that this is less of an issue than the potential to loose solder through wicking.

So my personal guess is that there are too many variables at play so i would assume the answer possible is “it depends but we do not know on which other variables”.

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Another argument I’ve heard is that when via’s are tented on both side they trap a bit of gass, and apparently this can get released violently enough during heating in the soldering process to cause problems.

I do not have a SMT production soldering strait so I can only parrot what I’ve read somewhere else.
I Do have noticed that sometimes with the plated through matrix boards the solder is “bubling” quite a lot from gasses coming out of the PCB.

Hi, what do you mean with this TAB or THERMAL pin. In my footprint editor it looks like this.

Shall i change the pad connection from “from parent footprint” to “thermal relief” for all 8 vias?

If you want to use a pad as a heatsink, then never use thermal reliefs, as they defeat the purpose of heatsinking.

The diameter of your via’s also look very small. Drilling becomes more difficult (and therefore possibly extra costs for you) when the diameter becomes smaller as about 3x the thickness, so for a standard 1.6mm PCB that would be a minimum hole diameter of 0.5mm (finished hole, the drilled hole would then be a bit bigger)

I also see that your via’s have pin number “10” while the pad has pad number “9”. That does not work. Give them all the same pin number.