Design Rules "lowest common denominator"

I see lots of numbers at the PCB fabrication service websites for “minimums” of things like minimum track width, minimum via drill size, etc.

That’s all very useful if you intend to push a design to the limit of the capabilities of any particular vendor.

But what if one just wants to design a 4 layer board which can fabricated at all (or most) major PCB services without modification? Are there any templates or advice on what design rules to use for that?

In my own case, I am doing a 4 layer board with mostly 0603, SOT-23 and SOIC (50 mil pitch) components and some through-hole headers. What would be reasonable settings to use which are far enough “relaxed” in specs that I don’t have to think about exceeding the capabilities of whichever vendor I end up choosing?

It seems like there’s no advice for what are reasonable design rules to use for particular component pitch sizes. I am aware of constraints that are physically based (like in the PCB calculator), but I lack any feel for what rules I should be using if my concerns are dominated NOT by power or RF issues but instead by the practicalities of manufacturing.

If it’s available from the 10pc/$10 chinese fabs, it’s a LCD.

Stick to 6/6 and 0.3mm drill and you should be fine anywhere

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This seems to be true for some manufacturers I checked, for “standard” or cheapest service. But 6/6mil is for 1oz copper; if you want to go thicker it may bump up to 8/8 or 10/10. The latter seems to be close to the KiCad’s default 0.25mm. If you want to be absolutely sure and you have space, use 10/10mil.

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I found one with Standard Quote options having larger value options: Min. Tracing/Spacing 0.2mm (down to 0.1mm), Smallest Holes 0.4mm (down to 0.1mm). I didn’t try if these affect the price, but I don’t know why they would be there if they didn’t. So 0.2/0.2mm and 0.4mm would be cheaper, and would be new “LCD” for basic copper thickness.

That was a long standing Chinese fab.

It still looks like the KiCad default values are conservative, safe “works everywhere” values, but unnecessarily large for most modern manufacturers and SMD technology.

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I found another one where 0.4mm (or rather 15mil) drill hole is required for the cheapest price.

It must be noted that these all values are for 2 layer boards. Clearance values may be different for inner layers, or multilayer boards may have different values altogether than 2 layer boards, depending on the manufacturer.

Still one important value is minimum annular ring which usually seems to be something like 0.15mm or 6mil. With 0.3mm hole it would make 0.6mm diameter for a via copper.

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…and one with 7/7mil trace/gap.

At the moment I would recommend for a 2 layer board and the standard 1 oz copper with SMD components:

Very safe values when space is not absolutely critical:
Trace/space: 0.2/0.2mm or 8/8mil.
Drill hole: 0.4mm or 16mil.
Annular ring: 0.15mm or 6mil (via copper diameter 0.7mm or 28mil).

Pretty safe, and if you need more space:
Trace/space: 0.18/0.18mm or 7/7mil.
Drill hole: 0.3mm or 12mil.
Annular ring: 0.15mm or 6mil (via copper diameter 0.6mm or 24mil).

Still quite safe, and if space is at premium:
Trace/space: 0.16/0.16mm or 6/6mil.
Drill hole: 0.3mm or 12mil.
Annular ring: 0.15mm or 6mil (via copper diameter 0.6mm or 24mil).

In practice vias are often more critical than trace/gap when space is limited. Therefore you may want to reduce the hole and annular ring size rather than trace/gap, but it may limit cheaper manufacturer options. Many can do 10mil or 0.25mm hole with their lowest price and the annular ring may be 0.13mm or 5mil. Wider traces are also better for current and heat, so 0.2mm or 8mil is a reasonable value even if via size is reduced.


Some capability lists are unbelievably unclear about the annular ring. It’s possible that a larger value, 0.2mm or 8mil, is “very safe”. That would make the via copper diameter 0.8mm or 32mil. But most can handle 0.15mm/6mil ring anyways.

Pretty safe minimum copper to CNC routed board edge seems to be 0.3mm or 12mil. Copper to V-score line’s center 0.5mm or 20mil.

Less critical are legend (silk screen) text sizes: character height 0.8mm, line width 0.15mm. That should be small enough with 0603 components and “very safe” clearance values which give room for the text. Manufacturers will probably let you try smaller without extra charge, you will just suffer if you can’t read the text. I have seen 0.6mm/0.12mm being so and so but usually readable even when the recommendation was 0.8/0.15.

Then there are the solder mask values: minimum bridge or dam or web (=“minimum width” in KiCad), and the solder mask pad clearance. You don’t have to care so much about them before deciding the manufacturer because in KiCad they can be set globally if needed. Often the manufacturer doesn’t even give values. They may decide the best values which suit their processes. Bigger values aren’t better, see Filled zone cuts corner of mask on square pads for some problematics. Some common values which are given are 0.05mm and 0.1mm, the latter may be said to be safe. Expected value for minimum width is also 0.1mm.

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The annular ring spec is literally just a derivative of the hole positioning error. most common fabs will quote this as about ±3 mil, and what minimum trace width your paying for, lets say 6/6 mil rules.

this means to avoid a break out you need at least a 0.08mm annular, however if your paying for 6/6 traces (0.15mm), your stuck to 0.3/0.45mm diameter vias as the smallest size that meets there specs.

While I would not push that far normally, Its not outside the realm of high yield, those holes need to be twice there quoted hole position spec to break out.


I always try to use suppliers that do electrical test and look out for the contact marks from the tester probes. I have seen signs of manual short removal on some boards.

Thanks eelik and everybody!

I was able to do my stuff with 8 mil tracks/spacing, adjusted vias and pour numbers until they “looked right”. DRC checks out and nothing looks insane.

I did notice in the PCB calculator something relating to “Board Classes” (screen shot below). Wasn’t able to find anything in the literature/google, but the table seems to suggest a standardization for track and via geometry. Does anyone know what is this table all about?

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