I’m ready to start routing a pcb and I need to set up net classes.
The board house I use provides a .dru file for Eagle. When I defined net classes, I had 0 mil drill and 0 mil clearance for all the net classes–I just defined trace width. I guess Eagle figured out appropriate sizes automatically based on the classes net width and the dru file?
Anyway, it seems for KiCad I need to define not only track width but also via size, via drill, uVia Size, uVia drill, dPair Width and dPair Gap for each net class. Can someone provide a reference on reasonable values for these as a function of track width?
Or, more generally, an eagle DRU to KiCad settings tutorial? I’m not looking for something automatic–I’ve just not had to worry about some of these details when I used manufacturer supplied DRU, but now I need to figure out the KiCad settings.
https://www.seeedstudio.com/fusion.html goes down to 4/4mill for “standard” and 2.5/2.5 mill for “custom” boars. Also nice, they specify a minimum width of 0.1mm for solder mask dams.
Apart from a general search you can also have a look at https://www.pcbway.com/ They specialize in hanging price tags on virtual PCB’s, and have therefore a lot of links to websites of manufacturers.
For the numbers of the other things such as micro vias, and the differential pairs, you only have to set them up if you actually use them.
Also: In the Board Setup there is a [Import Settings] button in the lower left corner. with it you can import these settings from another KiCad project file.
Note, the values that you get from the board houses are the absolute minimums that they can reliably (or will attempt at the price-point you select) manufacture. As a designer you may not want to try to meet those absolute minimums for a variety of reasons (ease of rework, suitability for quoting to manufacturers, current capacity of traces, voltage isolation, etc).
What I think is missing, generally, is knowledge of a guide for choosing via sizes based on trace widths. If someone has a link to a good evidence based written general purpose guide and/or calculator, please share. (I imagine there is an IPC or similar guide for this…)
I have a board house and understand their ground rules well. But, as you point out, they are just the minimums.
And, I understand how to choose track width based on current–been doing that for years.
What I think is missing, generally, is knowledge of a guide for choosing via sizes based on trace widths. If someone has a link to a good evidence based written general purpose guide and/or calculator, please share. (I imagine there is an IPC or similar guide for this…)
Exactly. really I just need via sizes based on trace widths. Better yet, just an automatic option that picks a default via size for the current trace width (like Eagle works).
The wanted via/drill size can depend on many things. KiCad can’t know what you need. Requirements for LEDs may be very different from requirements for high speed signals even though the trace width is the same.
EDIT: If we are talking about small indicator LEDs, the difference in in actual percieved functionality is probably zero if you choose between 0.2…0.5mm hole and correspondingly for example 0.5…1.0mm copper diameter. If you know that’s not the case, you should give an exact use case.
In 5.99 unstable nightly builds there’s a via calculator:
No,I’m not talking about small indicator LEDs. IR LEDS that are driven with 1 amp current, very small duty cycle
But, I’m not looking for help sizing trace widths. It was just an example-- what via size (and drill to use for 20 mil wide trace (that was chosen that wide to handle the RMS current it carries).
I’ll answer my own question, now that I’ve done a bit of online research
A little math shows that a drill hole the same size as the trace provides more conducting cross-sectional area than the trace itself. Actually, a via quite smaller than the trace width will have more copper cross section than the via. Minimum size via drill (12 mils in my case) is fine for a 20 mil trace.
So, it’s really just the annular ring (or via size in KiCad speak) that needs to be specified for each different trace width. And (apparently) the required size depends on how accurately located the drill holes are.
Not a big deal. Just required a bit of time researching details that have been “encapsulated” in a file provided by the board manufacturer.
If you make the assumption that copper thickness in the via is the same as on the rest of the PCB, via diameter should be (approx) track width/pi.
But is that assumption correct?
A usual process for making PCB’s is to start with 17um copper, drill the holes and make them slightly conductive, and then plate the via’s and the the whole PCB surface with an extra 17um copper, which suggests final copper thickness is 35um, but the copper in the via’s is only half of that.
Then there are a lot of other factors. Via quality is influenced by the quality of the bored hole surface, and faults in via’s are harder to inspect visually than tracks on the outside.
I’m not expert, but based I what I just read it seems that a drill size the same diameter as the trace would be quite conservative from a current carrying capacity, even if the copper thickness in the via is only 1/2 that of the traces.
Assume trace width = D. Perimeter of a via would be Pi * D. So, even with 1/2 the copper thickness, the via would be 50% more conductive than the trace, no? (Pi / 2 > 1.5)
I think bottom line conclusion is that drill size the same as trace width should not be an issue (as long as they are bigger than what the manufacturer can reliably do).
Regardless, I never use a single via for a high current carrying trace. I figure the redundancy is cheap.
Simple math seems correct. 1/1.5 = 2/3 = 0.6666 so with a hole diameter of 70% of the track width should still be ok. But for thin tracks its always limited by minimum drill size. And Indeed for high current tracks I also prefer redundant via’s.
The PCB_via.pdf document I mentioned earlier has some FEM analysis of via temperatures…
