Doubled up on the GND plane for the high current section.
Removed all via’s in the VCC net (I don’t like via’s in power nets).
Increased via size to 1.2mm with 0.6mm holes (No need for those tiny via’s.
Removed some dogbones, made others shorter (Shorter really is better because it makes interruptions in the GND plane smaller).
Made the area between the “sense” lines smaller (They are a sort of (but not really) differental (equal?) pair).
Moved the GND wires between the pins of U4 a bit. There was nothing really wrong with them, only if they form solder bridges between the pins it looks “weird”.
I only did a bit of cleanup. there are still some DRC issues. Most are for the silkscreen but some are violations for copper items.
This board will be part of a system that will need to pass CE. So if I wanted to add 2 layers with the intention to keep EMC to a minimum the process is (quoting Jonathon) add 2 layers in the board setup and create GND and VCC fills.
Having done that with a new version of the board here’s where I am.
Those layers are called ln1 and ln 2 and are sandwiched between the top and bottom layers
ln 1 being the upper layer is assigned to VCC
ln2 being the lower is assigned to gnd
As there are no Vias for VCC the only place the VCC layer connects to VCC is on the through pin of J4 as indicated by an arrow:
Whereas the Gnd layer has lots of connections to all the Vias that are already connected between the 2 outer layers. As per below (a few connecting vias indicated with arrows)
Because it’s easier, and as a habit.
In older versions of KiCad a zone could only be selected by clicking on it’s edge, and putting that edge far outside the PCB makes it easier to select it without accidentally selecting something else.
KiCad automatically enforces a clearance between the edge of the PCB and a zone. This clearance is either the normal clearance defined in the zone itself, or PCB Editor / File / Board Setup / Design Rules / Constraints / Copper to edge Clearance. (KiCad uses the biggest clearance).
Then you see that in the North-East corner, the zone is filled right to the edge of the zone itself, while at Edge.Cuts a clearance is respected.
This same clearance is also respected in your PCB.
In the end, the biggest difference is tat if there is ever a fault in the zone filling around the edges, then in your PCB the zone may get filled right to the edge of the PCB, while in my posted screenshot, a big pentagon will appear in the gerber files, which is a big red flag.
It is quite important that a zone does not get filled right to the edge because copper is a quite soft and gummy metal, and it may get smeared around and burrs may appear on the edge, and if this happens on multiple layers, then the finished board may have shorts here, or you can create a short when mounting the PCB in a metal enclosure.
If you want to go 4-layer (which seems excessive for this PCB), then you can delete all the tracks of the VCC net on the outer layer. This means that you can also remove most of the dogbones. You also have to create via’s to connect all the Vcc pins to the Vcc zone.
I do not have much experience with 4 layer PCB’s myself, but my best guess is that adding the right sort of filtering to the signals that come from and go to connectors is more important than adding even more GND.
I’m also having some doubts about the cutout in the GND layer I advised earlier. It was a “quick fix”, while keeping the GND layer intact and moving U1 (and surrounding parts) is a better solution.
But for the most part is is indeed simple as that. 4 layer PCB’s are much easier to design then good 2 layer PCB’s because you can easily assign a full layer to the GND zone. The biggest concern is to space via’s wide enough apart so long rows of via’s do not create big slots in the GND zone.
But if your PCB’s have to pass EMC testing, then educating yourself in EMC matters is pretty much mandatory. EMC testing is expensive, and a failed test even more so. You should not just rely on advise you read on some forum for matters like this.
Yes I know from past experience about the cost of products that fail, which is why I figure it cant hurt to put the layers in. And if I don’t and it fails the question will be ‘why didn’t you make it 4 layer?’ even if that is not the reason for it failing!
But it is worth while going through the processes I have here.
Yes, I did that.
Without that snake trail it is a very big gap in the GND plane.
My normal solution is to modify the footprint to use slightly narrower oval pads so the GND plane fills the area between each set of adjacent pins. but I was partly a bit too lazy to do that, but partly also because it was your design and I did not want to change too much about it.
GND is the reference to all signals so adding 2 inner layers you get smaller signal loops (signal track and its return path in GND) if the GND layer is the first under top.
If the VCC layer is only to be there and connected to something in only one place I suppose it can do more bad than good for EMC. You just added antenna that can resonate at frequencies resulting from reflections from opposite edges.
If you have paralel copper layers they should be shorted for high frequencies to work as single layer - to not form a resonance chamber between them. You short VCC with GND using ceramic capacitors.
It is not good idea to have the same shape for GND and VCC plane. The VCC plane should be smaller, I think. But - I have never designed 4 layer PCB.
About 1995 we had some problems with our products. We had one installation at the top of the plateau. Our devices liked to hung up if lightning struck at the building they were installed in. Those time I even didn’t heard the term EMC. I supposed that as I used ESD protected RS485 drivers I have done everything I can. I started to read a lot and when in 2004 we (Poland) joined EU and needed to EMC test devices and I went to EMC lab my devices just passed for the first time.
You shouldn’t feel for EMC problems in the dark. You should understand what you are doing and why. Start with reading articles I have posted their links here some time ago:
In my opinion for your PCB much more important is the right schematic design than adding 2 inner layers. I don’t remember what drives your PCB but was it designed with EMC having in mind. If not you need to do some work to take care of it or may be it would be better to design yourself everything from scratch.
Gents
I’ve done some changes to my gnd plane layout. I hope I am on the right track. I’ve separated Analog and digital grounds and they occupy different regions as shown. I’ve kept these on separate layers.
My question is how is best to tie these 2 separate layer ground planes together. They consist of the lowest 2 layers of the 4 stack board. Blue layer is analog gnd, orange is digital gnd.
Should the connection point be a single power track on the top layer connecting 2 Vias to each of these ground planes? Presumably a single Via could do the job? I really don’t know what is conventional or common practice.
I started it and intend to watch it sometime. Thought this was reasonably straight forward question and bypassed the rest of the video for now - guess that was a mistake.
There are probably sometimes compelling reasons to separate analog and digital GND, but as I know in most cases one single GND is better for EMC than 2 separated. Read articles I linked.
I think there are no rationale for this.
If you have one you have no such questions.
Any wire going between analog and digital part should have a return path near it. So one solution is all wires crossing the GND border close to each other and GNDs connected under those wires. The other solution is to connect GNDs with small capacitor near each wire crossing the border. Small capacitor gives the return path for high frequency components of signals but left GNDs separate for lover frequencies which were the reason to divide GNDs.
Typical rule in appnotes for A/D and D/A converters is that GNDs should be connected under that IC as one its part should be at digital side and the other at analog.
Separating analog and digital GND planes should not even be considered for <10bit or so ADC’s, and even then, the main key is still managing how currents flow through the GND plane, and that is mostly defined by the signals above the GND plane (above a few kHz) and DC resistance for DC.
Separating GND planes is always bad from an EMC point of view, and should only be considered when you really know what you’re doing. On top of that, leaving dog bones in GND planes on a 4 layer PCB is simply not done.
All that said, it’s mostly a theoretical excersize for this particular PCB because there is hardly anything on it, and it’s quite possible that your IC’s do not even have a particular fast edges.
And I repeat again:
For improvements, the biggest continuous GND you can get is better, and that means also closing the gaps between the pins of the 40p connector. After that comes filtering for all signals that get onto and go off the PCB.
These and more… Filtering is most effective as close to the disturbance source as possible so if you know that here you have a source you should consider filtering just here and not only at going off PCB.
That is why I just power all digital ICs through ferrite bead (I started to do so in previous century when they were expensive, but now it is not a problem). Digital ICs when switching its output they take fast and high current pulses from VCC and I just want that pulses to be not ‘visible’ at other ICs and at PCB power input. Imagine IC driving a differential signal pair going out of PCB. If it get any pulses at its VCC it sends it directly to the output line that just have high state at that moment.
I often route power tracks first. That way at least power is good, and the rest of circuit works better. Then critical or high impedance tracks.
My suggestion is to find out why a part is there. Parts which have some common task, should be close together. Like an IC and its power supply bypass capacitor. Of course you have an 100nF capacitor from power supply to ground at every ic.
The rest is usually not so critical.
