How do you place vias in 4 layer boards effectively

I have this not too complicated 4 layer board. When looking at it now, it might as well be a two-layer…

However. What is the most efficient way to pop via’s? I select the layer which has the ground plane than I pop the vias. This often creates vias without a net. So I made one ground via and started to do Ctrl C / Ctrl V. Than I draw tracks from pad to via (or vice versa)

afbeelding
I suppose I should use thicker tracks for this…

I don’t get the feeling that am I doing it like you are supposed to do?

Besides going back to 2-layer design, how are you supposed to do vias on a multilayer board?

Bas

One way is to start drawing a track, then depress v for Via and click a mouse button or [Enter].

Normal via’s always go though the whole PCB and it does not matter how many layers you have.

I don’t have experience with multi-layer PCB’s and am not sure how KiCad behaves if you place a “free” via on an area where muliple zones (on different layers) exist. Using Copy & paste is a valid way to make more via’s. Also note that each via has a property: Automatically update via nets. This is set when a via is added during drawing of a track, and it is not set for “free” via’s. When you use copy & paste, this attribute is also copied and pasted, so make sure you copy the right via.

I would too . . . I also try to avoid sharp corners such as those marked in this image . . .

image

You can add TearDrops (and fiddle with the settings). Quick example without spending time to dial-in any settings to make it pretty… No Plugin needed.
Tools>Add_Teardrops…

I was driving back home and all the sudden it hit me. An easy fix.

A 2nd groundplane on the top layer as well. This would allow you to just pop vias like you normally do. Than you don’t have to draw the actual traces. With a 2 layer board I’d normally use 2 ground layers and keep most tracks on the top side. I see no reason to do this differently

I do will take look into the teardroppes. I happen to be looking at a setting and I was wondering what it was.

Thnx for the answers. :tumbler_glass:

Bas

On a 4 layer board it is quite common to use both inner layers for GND. This improves signal integrity and reduces EMI because a prepreg layer (approx 100um) is much thinner then the whole PCB (around 1500um for the epoxy + glass fiber). Power is then routed as (fat) tracks along with the signals, and in some area’s one of the GND layers is sometimes sacrificed for extra track routing.

The intended use for teardrops is to strengthen the connections between pads and (especially thin) tracks. Some connectors have a relatively high insertion force, and this flexes the PCB a bit, and this can result in breaking a track of a pad. This is one example in which sharp corners have a detrimental effect on a PCB design. In a sharp corner mechanical stress is concentrated during flexing of the PCB, and cracks are formed more easily. Teardrops both strengthen the track connection because they widen the track near the pad, and they accommodate for a gradual transition which reduces the stress concentration further.

Amazing how breaking focus/concentration on a project allows you to re-imagine it.

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Each morning you have new ideas/solutions for the current project.

Besides the small spokes… it looks better IMO

The bigger picture with both inner and top ground planes displayed

This looks far better. (still need lot of work)

On a 4 layer board it is quite common to use both inner layers for GND.

IMO it depends what you want. The fasted things are hobby RC servo signals and 115200BPS serial communication. I have never done any high frequency stuff so I don’t know better :see_no_evil:

When going 4 layer I prefer to use one of the inner layer as power layer. Sometimes just 5V. Sometimes when I have more voltages I make more zones and try to place components to fit the zones best.

Amazing how breaking focus/concentration on a project allows you to re-imagine it.

You should know all the ideas that come to me when riding my bike to work. My mind can develop an entire line of products before the first schematic is born

Bas

It’s not always about clock frequency, you also have to consider edges and the rise times of those edges . . . and good practice is good for everything if you can get it to be your normal. :wink:

Let me correct that for you:
It’s NOT AT ALL about clock frequency, IT IS ONLY about edges and the rise times of those edges. It was not such a problem with old and slow logic (such as74LS). On more modern uC’s, FPGA’s etc, it is common to have several settings for slew rate limiting do reduce the noise generated by the fast edges by slowing them down. But all of this is much more of a concern if you have some commercial product and have to conform to EMC complicany rules.

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That boldface all-caps “correction” is some powerful bait. :rofl:

You should look here:

For me it’s not necessary. When you copper pour the GND zone, vias will be connected to the GND pad. Off course you will need GND zone in TOP and BOTTOM layers. It doesn’t matter if it’s a 2 or more layer.

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