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Yes this works.
- Select a single track segment.
- press u a few times to get more track segments.
- Press e to edit the track properties.
But overall, working with net classes is a much better way.
With net classes you can create groups of nets, and then assign default properties (for track width, clearance and via properties) which then become the default for those nets.
There is also a PCB Editor / Edit / Edit Track and Via Properties This dialog can work on a more global scale, such as modifying properties of a whole net, PCB layer or netclass, or it can be restricted to only work on a (previously made) selection. This dialog has more options and looks like:
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It has been suggested that I should have used a 4 layer PCB to minimise EMC and have the device pass CE.
Would you agree or is this board simple enough to not warrant it? It will be connected to a Raspberry pi though only signals for I2C and SPI will connect onto the board.
If it is necessary how difficult is it to turn it into a 4 layer design?
If you’re worried about EMC, then start by fixing the GND plane you already have.
In the last screenshot you posted there are still huge gaps in the GND plane under J4.
Going to 4 layers starts getting useful if one layer of routing is not enough and you need lots of tracks on a second layer, so that other layer can not have a decent GND plane anymore.
I’d say using a 4 layer PCB for this would be overkill, just fix the GND plane you already have.
Next step for improvement would be filtering of signals that go off-board, and that are in this case the 2 pwm signals. I have not looked closely at the datasheet of the IC that generates the PWM signals, I think it’s designed to be some kind of LED driver, I don’t know how steep those flanks are.
Depends. I don’t think it’s necessary here, but the price differences seem to get smaller and smaller.
Very easy, just add two layers in the board setup and then create GND and VCC fills on them.
However as @paulvdh wrote, it’s much more important to fix the existing fills on your board on the outer layers. Add a fil on the front layer as it seems to be missing. Add lots of stitching vias. Avoid strips and islands in the fill that could act as antenna. Fix these by moving your signal lines closer together.
And so on. I suggest to work on your design some more instead of focusing on advances stuff like 4 layers or CE tests. You’ve already made a huge improvement with your first redesign. Maybe start over once more and find some better routing. For example you see that the connection between U4 and the headers above are kinda awkward in your design. In your next iteration I’d route these towards the start so you can find a clean solution there. The power stuff towards the bottom seems mostly fine, however there’s also stuff that could be optimized. See how the bottom two pads of the 3 pin transistor(?) below U2 go into opposite directions? That can easily be made cleaner by rotating the component 180°. And so on.
Also as @paulvdh wrote, you’ll probably want to add filtering and ESD protection and similar stuff.
Just for fun I did a bit of cleanup.
- Doubled up on the GND plane for the high current section.
- Removed all via’s in the VCC net (I don’t like via’s in power nets).
- Increased via size to 1.2mm with 0.6mm holes (No need for those tiny via’s.
- Removed some dogbones, made others shorter (Shorter really is better because it makes interruptions in the GND plane smaller).
- Made the area between the “sense” lines smaller (They are a sort of (but not really) differental (equal?) pair).
- Moved the GND wires between the pins of U4 a bit. There was nothing really wrong with them, only if they form solder bridges between the pins it looks “weird”.
I only did a bit of cleanup. there are still some DRC issues. Most are for the silkscreen but some are violations for copper items.
2022-06-27_Servo_Interface.kicad_pcb (461.7 KB)
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Don’t know what to say - thanks!
Paul
I had meant to ask - why did you define the area of the ground plane beyond the edges of the pcb?
This board will be part of a system that will need to pass CE. So if I wanted to add 2 layers with the intention to keep EMC to a minimum the process is (quoting Jonathon) add 2 layers in the board setup and create GND and VCC fills.
Having done that with a new version of the board here’s where I am.
Those layers are called ln1 and ln 2 and are sandwiched between the top and bottom layers
- ln 1 being the upper layer is assigned to VCC
- ln2 being the lower is assigned to gnd
As there are no Vias for VCC the only place the VCC layer connects to VCC is on the through pin of J4 as indicated by an arrow:
Whereas the Gnd layer has lots of connections to all the Vias that are already connected between the 2 outer layers. As per below (a few connecting vias indicated with arrows)
Is it as simple as that? Are there any pitfalls I’ve fallen into?
Because it’s easier, and as a habit.
In older versions of KiCad a zone could only be selected by clicking on it’s edge, and putting that edge far outside the PCB makes it easier to select it without accidentally selecting something else.
KiCad automatically enforces a clearance between the edge of the PCB and a zone. This clearance is either the normal clearance defined in the zone itself, or PCB Editor / File / Board Setup / Design Rules / Constraints / Copper to edge Clearance. (KiCad uses the biggest clearance).
If you look at this screenshot:
Then you see that in the North-East corner, the zone is filled right to the edge of the zone itself, while at Edge.Cuts a clearance is respected.
This same clearance is also respected in your PCB.
In the end, the biggest difference is tat if there is ever a fault in the zone filling around the edges, then in your PCB the zone may get filled right to the edge of the PCB, while in my posted screenshot, a big pentagon will appear in the gerber files, which is a big red flag.
It is quite important that a zone does not get filled right to the edge because copper is a quite soft and gummy metal, and it may get smeared around and burrs may appear on the edge, and if this happens on multiple layers, then the finished board may have shorts here, or you can create a short when mounting the PCB in a metal enclosure.
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If you want to go 4-layer (which seems excessive for this PCB), then you can delete all the tracks of the VCC net on the outer layer. This means that you can also remove most of the dogbones. You also have to create via’s to connect all the Vcc pins to the Vcc zone.
I do not have much experience with 4 layer PCB’s myself, but my best guess is that adding the right sort of filtering to the signals that come from and go to connectors is more important than adding even more GND.
I’m also having some doubts about the cutout in the GND layer I advised earlier. It was a “quick fix”, while keeping the GND layer intact and moving U1 (and surrounding parts) is a better solution.
But for the most part is is indeed simple as that. 4 layer PCB’s are much easier to design then good 2 layer PCB’s because you can easily assign a full layer to the GND zone. The biggest concern is to space via’s wide enough apart so long rows of via’s do not create big slots in the GND zone.
But if your PCB’s have to pass EMC testing, then educating yourself in EMC matters is pretty much mandatory. EMC testing is expensive, and a failed test even more so. You should not just rely on advise you read on some forum for matters like this.
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Yes I know from past experience about the cost of products that fail, which is why I figure it cant hurt to put the layers in. And if I don’t and it fails the question will be ‘why didn’t you make it 4 layer?’ even if that is not the reason for it failing!
But it is worth while going through the processes I have here.
Paul
If I unfill the original ground plane I get this. Was that winding ground track something you added?
Yes, I did that.
Without that snake trail it is a very big gap in the GND plane.
My normal solution is to modify the footprint to use slightly narrower oval pads so the GND plane fills the area between each set of adjacent pins. but I was partly a bit too lazy to do that, but partly also because it was your design and I did not want to change too much about it.
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If you’re concerned about EMC, then this is a very good video. It’s a tad long (over two hours) but it’s worth it.
at around 1:40:00 some 4 layer stackups are mentioned, and the (simplistic) conclusion is more ground is more better. 
GND is the reference to all signals so adding 2 inner layers you get smaller signal loops (signal track and its return path in GND) if the GND layer is the first under top.
If the VCC layer is only to be there and connected to something in only one place I suppose it can do more bad than good for EMC. You just added antenna that can resonate at frequencies resulting from reflections from opposite edges.
If you have paralel copper layers they should be shorted for high frequencies to work as single layer - to not form a resonance chamber between them. You short VCC with GND using ceramic capacitors.
It is not good idea to have the same shape for GND and VCC plane. The VCC plane should be smaller, I think. But - I have never designed 4 layer PCB.
About 1995 we had some problems with our products. We had one installation at the top of the plateau. Our devices liked to hung up if lightning struck at the building they were installed in. Those time I even didn’t heard the term EMC. I supposed that as I used ESD protected RS485 drivers I have done everything I can. I started to read a lot and when in 2004 we (Poland) joined EU and needed to EMC test devices and I went to EMC lab my devices just passed for the first time.
You shouldn’t feel for EMC problems in the dark. You should understand what you are doing and why. Start with reading articles I have posted their links here some time ago:
In my opinion for your PCB much more important is the right schematic design than adding 2 inner layers. I don’t remember what drives your PCB but was it designed with EMC having in mind. If not you need to do some work to take care of it or may be it would be better to design yourself everything from scratch.
Gents
I’ve done some changes to my gnd plane layout. I hope I am on the right track. I’ve separated Analog and digital grounds and they occupy different regions as shown. I’ve kept these on separate layers.
My question is how is best to tie these 2 separate layer ground planes together. They consist of the lowest 2 layers of the 4 stack board. Blue layer is analog gnd, orange is digital gnd.
Should the connection point be a single power track on the top layer connecting 2 Vias to each of these ground planes? Presumably a single Via could do the job? I really don’t know what is conventional or common practice.
I guess you thought that 2 hour video about GND planes and EMC was too long for you.
I started it and intend to watch it sometime. Thought this was reasonably straight forward question and bypassed the rest of the video for now - guess that was a mistake.