Question is in the title. I don’t want to waste time and money getting something that won’t work.
I’m confident in my schematic. I ran the error checker, and it passed without flags (after a couple minor tweaks). https://ovo.fyi/lorem-ipsum/ https://ovo.fyi/temp-mail/
I’m planning to send it to JLCPCB, unless anyone has a better idea for fast turnaround at a reasonable price.
Make sure you can buy all components you have selected. (Really double check! Especially the availability of ceramic caps is still questionable at this point in time. The MLCC shortage is not yet over. And also check that you can buy it at the quantities you would like. It is not fun to discover that you can only buy a specific part as a full reel of 1000 parts.)
Double check all symbols and footprints against the datasheet or relevant industry standards. (There is a lot of tolerance here if you are not interested in squeezing out the optimal yield.)
Check that through holes are large enough to encompass the tolerances of your pcb manufacturer and the tolerances of the component lead.
Make sure that you did not confuse top from bottom view for the pin assignment.
Run ERC on the schematic and make sure no error or warning given by it is a false positive. (Passing ERC is not a guarantee for your system to work)
Make sure every IC you have is supplied (Especially dangerous if you use multi unit symbols. KiCad does not check if you placed all of them.)
Make sure you setup the DRC rules such that they fit your PCB manufacturer.
Run DRC and check “list not connected” (Here i would suggest you do not allow any errors unless you are really sure it is still ok.)
Check your copper planes if you have them. They are not a magical thing that ensures good ground (or whatever net you gave them) all over your board.
This assumption only holds if the plane is uninterrupted (hard to achieve on a two layer board.)
And there is another question that we can not answer. Does it even matter for your application? (Do you have high frequency or fast du/dt signals? Do you have “high” current paths? …)
On a two layer board check where you have interruptions. Can you get rid of them in some way? If not: Do you still have good connection between different points that need good ground? (This is an art in of itself.)
If you have a >=4 layer board then i assume you have a full layer for this plane. -> make sure no THT connector or no set of vias creates an interruption in that case. (A row of through holes can easily create a slot in your plane. Check the planes clearance and min width settings if this is the case. If playing with these parameters does not solve the issue then either select a different connector, decrease the copper restring or move the vias apart.
Rene pretty much layed it out!
PCB making is an absolute art in itself. It’s not just the making of a board. Anyone cone throw something together. No big deal. There is tremendous knowledge in electronics of varying fields required. Lot’s of experience.
Been doing boards since the eighties in a variety of complexity. Single, double, multi 4+. High spec boards for mission critical where error can lead to fatalities. All that. There are no two boards the same. With every board the issues are different anew. That’s the challenge.
DC, AC low or high frequencies, low or high currents, high accuracy measurement designs, is where the challenges lie.
In any case make sure you have got the parts or you can get them for sure otherwise you are in for it.
Another good guide is to read the parts manufactures specification documents. And I mean READ them! It’s more important than you might realize. Many of them provide these days layout recommendations as well which are critical in many situations to follow indeed.
Good look.
I copied Rene Poschi’s checklist and made a desktop folder for it. I just sent my board out to be made without having all the parts on hand.
People new to PCB design often make similar mistakes by lack of knowledge of PCB design in general, and limited knowledge of KiCad itself.
Sometimes I’m in a mood to do a review and even edit boards uploaded to this forum.
You may find it enlightening to read through them.
Two of those examples are:
https://forum.kicad.info/t/seek-review-my-first-design/15510
https://forum.kicad.info/t/please-check-my-first-pcb-design-in-kicad/15409
There are also tutorials about good pracices about PCB design on the 'net, and expensive and extensive books about EMC, “design for manufacturability” and other related topics.
OK, you obviously start by specifying reasonable Design Rules, and make sure your board passes DRC. Even with programs that allowed a user to over-ride DRC squawks I always worked to produce a board without errors or warnings.
A closely related source of errors (and not limited to inexperienced designers!): Make sure that the footprints, schematic symbols, and packaging for your specific part are in agreement. Does “Pad 1” and “Pad 2” on the footprint agree with the orientation of “Anode” and “Cathode” (for diodes), or “Pos” and “Neg” (for polarized capacitors)? There are workarounds for those mistakes - just install the part backwards, and hope that nobody doing rework or repair notices - but the really insidious errors happen with transistor packages. The TO-92 and SOT-23 packages are notorious for having “B”, “C”, and “E” assigned to different package pins.
View your Gerber files in a Gerber viewer. I usually do this two layers at a time, choosing the pairs so the displayed image will emphasize certain types of errors.
Is everything inside the Edge.Cuts outline? Pay special attention around slots or cutouts.
Do all the places that should have holes, actually have holes? Do any holes show up where there shouldn’t be a hole? My most common mistakes in this topic involve placing the board’s mounting holes, or the non-electrical holes used for component mounting screws, alignment pins, etc.
Do you have proper registration between top and bottom copper (or any other layers)? It’s pretty hard to mess this up, until you start making fancy pad shapes.
Does the soldermask align correctly with copper on all layers? Typically there is a gap of a few mils (0.1mm, more-or-less) between the soldermask and the exposed copper. Some board fabricators will “correct” this for you but I prefer to specify this the way I want it done, and let the board fabricator tell me he can’t do it that way (if necessary).
Do the paste apertures look correct (if a stencil will be made for a reflow soldering process). This is an area that still falls someplace between “art” and “astrology” on the scale of technical progress. Talk with the folks in Manufacturing about how the apertures should be made, for best results with the particular combination of stencil process, solder paste and flux, and reflow machinery they will use.
Look at the silkscreen layer. CAREFULLY look at the silkscreen layer. REALLY, carefully, look at the silkscreen layer. Did you remember to select “Plot footprint references” (and/or “Plot footprint values”) when you plotted that layer? Does ANY of your silkscreen fall on bare copper areas? Of course, you can always avoid the problem by using “Subtract mask from silkscreen” when you plot Gerbers - and some vendors will do this automatically, even if you don’t request it - but it can lead to some ratty-looking silkscreen on finished boards. Unfortunately, the silkscreen is probably the least critical layer affecting board performance (as long as it doesn’t create soldering problems by covering bare copper), but it is often the first thing a customer will notice when judging the “quality” of a board.
Dale
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