Please check my first PCB design in Kicad

Hi all dear members
I have designed my first PCB in Kicad. It is such an isolated interface board with capability of CAN & RS485 & RS232 communications and is free for using every one who will be interested in it :slightly_smiling_face:
I really appreciate any kind of recommendations and advice for better design and really eager to get your valuable comments .

My PCB is in below path:

https://drive.google.com/file/d/1j-0jbBqKXFMiP2X4WuIMjI6thlOXToNT/view?usp=sharing

Thanks you all
Best Regards

I recommend switching to KiCad version 5 and porting the project to it.

The silk layer is bad. Use the 3D view to see how it would look like if the silk screen were printed on the board.

Lower left corner of the outline is bad, it’s easy to fix.

You have used footprints for stitching. In v5 you can easily use vias for stitching. Create array of vias or select a grid which has the right pitch for your stitching. If you still want to use footprints, at least create a new footprint for stitching which doesn’t have Adhesive or Mask layers enabled and which doesn’t have visible reference designator.

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Ohhh thanks Eelik
I will download kicad 5 and will edit it. Actually I dont want to print the silk screen for this prototype board because of this I didnt order the designators

OK. Check out the FAQ for converting the project to v5 if/when you have problems. https://forum.kicad.info/c/faq

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Hi @Sara-

Overall, this is a passable first board. There are some things you’d want to look at to ensure that you mean to do them. I’ll assume that you are limited to a 2 layer board for this design. If you are not, 4 layers are not substantially more expensive and would simplify your design.

  1. Power. Your VDD3v3 net goes through a lot of changes (layers, trace widths, etc). I’m attaching an image of the net highlighted

Note that you have a lot of space around the edges where you could route a power bus and eliminate many of the extra vias in your power routing. Alternatively, since you are supplying power to many elements, you might run a single bus down the center and branch power lines out. The key is to remove as many of those vias as you can and keep the lead traces thick until they can’t be anymore.

  1. (a) On your input section:

This is U3 in your system that takes 5V in and outputs 3v3. This is problematic because pin 1 is your power input. Pin 3 is only your inhibit line. And all of the power will need to return to pin 2. I’d recommend re-working the placement of this.

  1. (b) You can improve the placement by reducing the number of capacitors on this.

Bildschirmfoto_2019-02-25_07-57-43

It is detrimental to stack capacitors of low ESR next to each other[1]. They create resonances between each other that can cause high impedance for specific frequencies. This allows noise at this frequency into your circuit where it would not have existed with a single capacitor value.

The exception to this is when you use a high ESR capacitor for bulk decoupling (like an electrolytic at the input) in addition to the small ceramics of 10-100nF near the input pins.

  1. Grounds. The two ground planes should be connected in more places. I don’t think that the ring of vias around the outside is doing anything for your circuit as current would need to flow out to the edge and then back to reach the return point. Here is an image of the middle of your circuit, focused on just the ground.

Note that there are long loops and fingers in the ground plane with no vias to connect it to the top ground plane. This will create resonant antennas as current flows preferentially through one plane, causing current to flow in the opposite direction in the other.

Overall, this looks like a functional circuit and by far the best first KiCad circuit I’ve seen here. With a little polish, this will be a very nice unit. Well done!

[1] https://www.cypress.com/file/135716/download

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I’ve just opened the design in KiCad V5.0.2 and all schematic symbols get remapped without problem. The PCB also loads without problem.

Getting thrown a design in your lap without any background or intended use is … a bit difficult. When I start looking deeper into the design it gets fuzzier all the time.

I’ve spend some time in writing down some random remarks in the order I saw them.
It will probably take you some time to digest them. Don’t try to do it all at once. Take one or a few items at a time.

Edit: I wrote my post independent of Seth_h, there is overlap.

I see quite a lot of things I like, bunch of things that can be improved (No wonder for a first design) and a whole lot of things I do not understand. Can you tell us a bit more about the intended use of this design?

The overall design looks like a development board, but for a development board I would expect connectors on all unused I/O pins. The pins on the STM32F407VGTx are pretty small, and it is a nuisance to solder wires to them later. You also have plenty of room on the PCB to add some 0.1" breakout headers.

I like the grouping by functionality on the schematic. Did you follow the guidelines from the EEvblog video there? I like the fat blue text for different function blocks, but the blue dotted lines are a bit overkill, I tried that once also, and the tend to get moved and redrawn a lot, which is mostly a waste of time.
You have a clear isolation barrier on the PCB, which is very good. But I would like that same barrier on the schematic. If you want to blue dotted lines on the schematic, then use it for the isolation barrier. For example, I think these voltages are on different parts of the isolation barrier:


(I removed the bold attribute from one of the labels, makes it easier to read).

You have a separate block with connectors, and it is not clear what they do. It is much more logical to put the connectors with the function blocks where they belong. Put the RS485 connector in the RS485 block.

RS485
Use a more strict signal flow from left to right.
Start with your RxD & TxD modbus labels on the left. Draw a dotted line as isolation barrier right through your ADM2485 and design the symbol in such a way that the different voltage domains are on separate sides of the IC.
Then draw the output section with TVS and resistors on the right side, and also put the connector there. From the “RS485” section it looks like the VDD5v_iso and GND2_iso are the outputs (inputs?) of the circuit. You have to search and follow A+ and B- labels to see those are connected to the external connectors.
I am not sure what the 10R resistors do with the signal integrity of the RS485 data, but they may be a good idea. If you put the PSM712 between the 10R resistors and the RS485 driver chip they work more effectively.
Beware of the RS485 termination resistor (R22) and the Bias resistors (R19 & R23). These should not be placed on every board. You should have a note about that on the schematic. Have a look at “10 ways to bulletproof RS485”
https://duckduckgo.com/?q=10+ways+to+bulletproof+RS485&t=opera&ia=web

It is unclear to me what your “level shifter” block does without carefull analysis of all the labels. Make more use of wires instead of labels. For example, use labels for the RxD and TxD lines from the processor, and then connect the level shifter, RS232 driver and connector with wires (in logical order, signal flow from left to right).

USART3 (Rx & Tx) are both connected to 3 semi conductor pins. (uC, RS232 chip, Level shifter). Looks likely to be a short, but I haven’t looked too deep in what the components do.

I like the TVS diodes.
I like the ferrite bead, but I want to see more of them. Especially where te power comes into the board. The uC is easily upset by (very short) spikes, and these short spikes go right through the voltage regulator.

Reset switch:
100nF directly shorted with a switch that can probably only handle 50mA or so is not a robust design. For a reset switch that only gets used occasionally this is less of a problem than for example a rotary encoder, but it still is bad practice. Assume such a small ceramic capacitor can deliver a 10A peak current.

Resistors:
Youve added “R” to all the values. Not an error, but unusal. It is more common to simply use a value of “10k” for a 10k resistor. Personally I use “R” only for small resistors (< 1k Ohm.) For example “4R7” for a 4.7 Ohm resistor or “R22” for a 0.22 Ohm resistor. I try to avoid dots in values, but nowaday’s when stuff is getting printed on paper less as it used to be this becomes a lesser issue.
Youre using suffix “K” for kilo (Except for R6), but SI suffix is lower case ‘k’ for kilo.
https://en.wikipedia.org/wiki/Metric_prefix
I would give R19 & R23 a value of “1k2”.

Talking about a voltage regulators…
The LD3985xx is a very small voltage regulator and gets overheated quickly. It also does not have a good connection to the GND plane. Normally the GND plane is used to give such SMD components a bit of extra cooling. A good Thermal connection to the GND plane can easily double or even triple the maximum current such a small voltage regulator can handle before it overheats. A bigger voltage regulator such as the LM1117 seems a better choice. But have you considered using a small SMPS?
With an SMPS ( I think I like MP1485 but it’s just an example) you can use any input voltage between 5V and 24V. The inductor in the SMPS also keeps electrical noise on the external power supply lines away from the Vcc output to the processor.

You’ve made all the text of the labels bold, but for small text that does not improve readability. I think it’s better to use bold text sparingly for some important things.

Why such a monstrous big Processor?
Why Can + RS485+UART?
Why no USB?
Why a DS3231? (STM32 has built-in RTC clock with battery backup).
Why all those isolated interfaces? They make a first design relatively expensive, especially if you use so many on them.
Why a 20MHz oscillator? I’m not familiar with PLL settings of this processor, but 8MHz seems to be a “standard” for STM32. Ans why an crystal oscillator instead of just a crystal?

Making more use of power symbols (For all Power Connections) instead of labels make your schematic easier to read.

How do you intend to manufature this board?
Double sided boards, trace widths of 0.3mm and all the via’s are hard to do at home.
If you have the board made by a PCB fab you usually get the silk screen for free.
Silk screen is a very usefull addition during asssembly and finding faults on board. All those SMD pads make you dizzy without a silk screen during assembly. I wanted to have a look at the routing of the ESD diodes. The current paths (Also through the GND plane) must be kept away from electronics, but because you have not paid attent to the silk screen it makes it hard to see which components is which. Some manufacturers also print the silkscreen over pads if it gets printed, which makes soldering hard.
Silkscreen is also usefull for labeling pins of connectors, especially for individual screw connector pins.

You have made the Zones for the GND planes the same size as the board outline.
This is not so good. It makes the zones harder to select. KiCad should always respect a clearance between the board outline and the edge of the zones. It is better to make the zone 1 or 2mm smaller than the board. Alternatively, I often make the zones a lot bigger then the board outline, and with some slanted or jagged edges. If anything then goes wrong during Gerber generation you see it immediately. With making the zones and board outline the same, you risk having the zones to the edge of the board, which can lead to manufacturing problems (Shorts around board edges).

The GND Zones look reasonable, but they can be improved. You have no copper under the processor itself, and the processor is the most sensitive to voltage differnetials. I’m not sure about the STM32F407, but I think the core of the STM32 processors runs at 1.5V or so and only the I/O pins get 3V3. This means you want a better GND plane under the processor, with no interruptions. You can very easily do that by clicking on the Red zone on F.Cu, then “e” for Edit and making the clearance a bit smaller (From 0.508 to 0.4mm will do). This will have the GND plane sneak through the corners of the STM32 and fill the area beneath it. As a second step move the via’s in the square under processor to the side. You want as much copper there as you can get, and it must be connected directly to all the GND pins of the processor.
You can even easily remove most of the vias away from that important square. For example, the traces for the rs232_Leds go under the processor, then to a via, and then the go right back to the pad they came from. Ideally you have 2 copper squares under the processor. One for GND and one for Vcc, and the decoupling caps are as close by as you can get them.

You also have the connector J4 directly connected to the GND plane (although not connected very solidly). Preferably both GND and VDD5v_68K go through a common mode filter (or at least ferrite beads & ceramic capacitor) and then only connect to the voltage regulator section before a connection to the GND plane is made. Keep external noise away from the GND plane.

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May be RS485 is used mainly as receiver here :slight_smile:

If transceiver has a weak ESD protector, and outside you have a strong surge protector they assure that high current goes through this external protector and not through internal.

No.
PSM712 is specified for 20A (8/20us) but 10 Ohm resistors rather not.

I use only if dot in Ohm value is needed so: 0R22, 2R2, 22, 220, 2k2, 22k, 220k, 2M2, 22M).

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A note about the fuses.
What sort of fuses are you using?
They seem to be SMD / non replacable.
I assume you want to use PPTC’s.

PPTC’s are pretty fragile during hand soldering. I’ve had turned some into a mushy goo while soldering, especcialy when you made a little mistake and have to rework them.
The THT PPTC’s tend to be easier for hand soldering, especially if you have a few mm of wire between pptc and the solder connection on the board, they do not become so very hot.

Instead of the 10 Ohm resistors for RS485 you can also put PPTC’s there. These will protect against accidental DC voltages upto the rating of the max PPTC voltage, but for this to work the PSM712 must be behind the PPTC’s.

Piotr is right that an 0805 resistor can not handle 20A DC, but the current spikes are short. PSM712 is also only rated for short pulses. For protecton devices like these resistors it is also common to use bigger packages such as 1206 or 2510 which can absorb more energy before they get overheated.

When you want to be really cautios you should also include “spark gaps” on your pcb.
https://duckduckgo.com/?q=“spark+gap”+pcb&iax=images&ia=images

I just had a brief look and I’m kind of surprised that there are no footprints for spark gaps in Pcbnew.

Edit:
With “spark gaps” I mean the jagged PCB traces with no solder mask over them. I do not mean the “gas discharge tubes”. The “spark gaps” as jagged PCB edges are essentially for free, and they can be very usefull. Just as purposefully thin traces designed to be used as fuses. If combined with SMD pads the fuse can be easily repaired if need arises.

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I design 2 layer PCB in such way that I have all connections except GND on top layer, and whole bottom is GND.
Imagine digital signal connection from source to load goes 3cm up and then 4cm right. The DC back current would go back directly by third side (5cm) of triangle, but the higher is the digital signal component the more it likes to go back directly under the original signal track. It is very good as the area surrounded by the signal is smaller = much less emission and much less sensitivity. Understand the sorrounded area as receiving/emission antenna. If current can go back under the track the area (looking from top) is 0 (looking from side the PCB thickness becomes important).
That works if the back current has a copper to go back as he wonts, but at your PCB it has not.

Yellow line is as I suppose one of digital signals travel on your PCB (not sure, but I don’t see the shorter GND way to go back). I assumed the GND is the reference to signal, but when GND connection is not good it can also use VCC connections jumping betwean GND and VCC by blocking capacitors.

For QFP microcontroller footprints (I don’t use such big as here) I go with VCC through one corner under the IC and go out through all others to another components. The GND pins I via (under IC) to GND layer. To each VCC/GND pair I attach 0402 100nF and if have place via to GND also near C (but it is not necessary). To make it easier I have modified all my QFP footprints to have last pads near corners a little shorter form inside, and with corners cutted. The rest place under IC I fill with GND.

Go with VCC that way and it is possible that you will be able to make all connections without any via (except GND). That is because going with VCC to all VCC/GND microcontrroller pairs is what disturbes all other signals. If some lines crosses I use other microcontroller pins if possible (I use ATXmega where for example SPI pins can be swapped by software).

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It is specified as 600W for 20us pulses. 20us is the surge current pulse and it is not short in my understanding. ESD defined in ns pulses are short.

Ror RS485 termination I don’t use bigger but Pulse Proof resistors:
http://www.vishay.com/product?docid=20043

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I was using them in previous century. But their parameters change dramatically in dependence of humidity and with dirt collected by PCB during years of working (specially in industry environment).

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@Piotr, Tnx for the link to the pulse rated SMD’s.
100W for an 0805 is quite impressive, even if it’s only during 10us :slight_smile:
20A through 10R = 4kW and even a 2512 cops out by 2kW :roll_eyes: But those are serious pulse ratings. I still think it’s better to put the PSM712 behind the resistors. In that case under gross overload the resistors blow out, but the rest is still protected.
If you put the PSM712 in front and it gets destroyed, then the ADM2485 gets destroyed to.
Have you ever tried those spark gaps with a milled slot in between? That shoud take care of contamination in an industrial environment.
Return paths for currents are important for high-speed design, but U8 is an RS232 transceiver and it don’t matter much. The return current transients also go just as well through the decoupling caps and use the Vcc plane if it’s closer by. They are not choosy in that aspect.

I’m also afraid we’re getting carried away too far for Sara’s first design. I think we’ve covered most of the basics and it’s probably better if I stop typing and give her some time to digest it all and respond.

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In Piotrs screenshot I noticed the big gap under IC1, which is unusual because it destroys the GND plane at that location. When I noticed it was the DS3231 I had a vague memory about not putting GND’s under them because currents through the GND under them can cause time deviations.
From that aspect putting it between the power connector and the uC is the worst placement on the board. It would be better in this aspect to put the DS3231 in a quiet (electrically speaking) corner of the board and then route the I2C signals to the uC. I1C signals are low speed slew rate limited and routing is not critical.
The horizontal trace that connect all the GND pads of that chip is not a real board issue, but something “customers” easily “complain” about, because they think those shorts should not be there. (Oooh, it’s a short, the board must be badly soldered).

I also see a silk screen mark @pin 10 Silk screen is often not printed very accurately and your pin 10 mark may shift to between pins. Sometimes those markers are put directly into the copper.

(I’m afraid I’m rambling ever more about ever smaller details).

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Your right to think what you wont :slight_smile:

It could be thinking many, many years ago when “the rest” could have a huge cost. Now I think only important is: do after getting surge the device is working or not. Point. No more questions asked.
During EMC tests if device after surge needs be repaired then test is failed - you can’t sell it.

If destroyed then the decision is: take stronger elements. I am using SMB 600W transils plus 1A bridge, but I am using not isolated RS485. In isolated you don’t need so strong protection as there are really no serious pulses comeing betwean A and B. My solution takes much more PCB space but less then isolation and has lower capacitance. I designed RS485 front 10 years ago and since then didn’t change anything.
SMB 600W is not the same as PSM712 600W !!!
I am using only true fail-save transceivers = no polarising resistors. We had these resistors in our system designed about 1995. There is no way to make all firms installing your system to do it correct. Really, really no way.
We assume up to 100 devices on our 485 and we don’t use the technic of asking each one in sequence. If you need to tell something you tell. It is much faster then wait until asked. If no device has anything to tell then our RS485 is completelly quiet.

No it was so long ago, that I didn’t know that I can define other opening then just the round whole.
I think spark gaps are only acceptable in very budget projects.

Have you ever seen 20 years old CRT TV inside?

You are right. The better example could be lines to RS485, but there return paths were better :slight_smile:
I just wonted to show how to look at that. I have heared that it happened that 1kHz signal made device to have to much emission at some handred MHz range as the dU/dt is more important than frequency and current ICs have high dU/dt at their outputs.

To late. I didn’t read the whole before answering :slight_smile:
The more we will say the better will be her second design. Learning never enough.

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Thanks for your useful link

Hi Seth_h
Hi paulvdh
Hi Piotr
Hi eelik

Thanks so much for your great comments I have learned a lot from your valuable comments. I will edit my PCB as you said and upload it soon
Thanks a lot for your attention and time you took on my project
I like Kicad because of it’s great community forum which I can learn a lot from the expert members like you all :slightly_smiling_face::hibiscus::hibiscus:

The others are likely much better at Kicad than I. However I do suggest you make the via drill sizes larger. Currently they are at the typical “minimum” board houses will accept. However If you make them even slightly larger, the result is more copper connecting the layers. And there is no down side.

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JohnRob is rigth, Some via’s have only a 0.4mm hole for via’s and that is pretty small, which might lead to more expensive boards. 0.6mm would be fine though.

If you have this board manuactured and you make Gerbers & a drill file, you can look into the drill file if you’ve missed any of the very small via’s. There may be easier ways to check this,but the Drill file is the final check.

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I ve not sent it to the manufacture yet. The reason of small vias was that because some tracks were just 0.3mm and I thoughut its better to use smaller vias for these kind of traces
Thanks

KiCad will draw a copper ring around the vias (“annular ring”) to mike them wide enough.This is also needed because just like any mechanical operation, drillig is not perfect and has some tolerances. Drilling on an edge of the copper might bend and break the drills.

I had a little problem viewing your PCB in the 3D viewer, and when zooming in on the corners I noticed the board outline looks like:

For a rectangular board you should have 4 lines with the end points perfectly aligned. I also noticed that your LED’s and resistors for the LED’s are not “perfectly” aligned. This is not a problem on it’s own, but it is very easy to align things if you work on a coarse grid.

I usuallly place the board outline, mounting holes, and components on a coarse grid, and do the routing on a very fine (or in practice no) grid.

When you start looking for it you start seeing it everywhere :slight_smile: Zone boundaries are also not rectangular. This is also just cosmetic, but on a coarse grid it is very easy to get them perfectly rectangular, while on a fine grid you’re struggling to get them almost rectangular.

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