7.0.0-nightly - nets and netclasses

Hi all, I was wondering, whether I might be missing something trivial, but I don’t find the netclasses in the latest nightly build. This is what my board setup looks like:

although I have altoghether 10 nets on the board. (J102-Pad1, and J103-Pad1 come from the original board file that I created with 6.0.10, and I entered J104-Pad1 by hand.)

Is this a known problem, or something that can be tweaked in the settings?


It looks the same for me in V7.0.0-rc1 and I’m quite surprised by that. I’m not very familiar with V7, but V6 has a few boxes for Filter Nets and Assign Net Class in that location.

In V7 I do not see my nets in the Board Setup / Design Rules / Net Classes, but I can see them in Inspect / Net Inspector.

That’s right, but the inspector is for, well, inspecting only, so you can’t really change properties there. But many thanks for confirming!

Yes, I know, but at least it confirms the netlist itself is still present.

The UI for assigning nets to net classes has changed for V7, now we use pattern matching to assign netclasses rather than the old UI with a list of all nets.

Note that in the original screenshot, anonymous nets (unlabeled nets) are shown – they have names like Net-(J102-Pad1). These net names are unstable and so it’s not recommended to try to put any anonymous nets into a net class.

Something like this


Indeed, If I click on the plus and then type: /PB* then I see a bunch of nets fitting to that pattern:

This is however a PCB imported from a Previous KiCad version, and it appears the previous netclass assignment is lost although the nets themselves appear to retain their width. Unfortunately I’m lacking the focus to to figure out what is happening here, but it does not seem very intuitive. I guess it’s back to reading the manual…

Except that does not help much either. Looking at the master branch of the documentation still shows the old method.

So, then it means that one has basically fill in the list by hand. I understand that you can use pattern matching, but that still means that, in a sense, there is no overview of the nets. Thus, you have to know from somewhere, what the net names are.

I don’t quite get what you mean by the Net -(J102-Pad1) being unstable. Nothing prevents me from assigning exactly that name, either out of whim, or convenience, and KiCAD should be able to handle that.

I agree. There are always complaints about KiCAD not being intuitive, but I found the handling of netclasses quite self-explanatory in version 6.

If you re-annotate J102 and it gets a new name, suddenly that net won’t be in the netclass anymore. If you add a component to that net that has a refdes that sorts before J102, suddenly that net won’t be in the netclass anymore.

Oh, OK, so you are saying that Net - ... is sort of like a reserved keyword, and one should not use that.

That is an anonymous net name, it’s what you get if you wire things up in a schematic but do not use net labels anywhere. It’s a real net, but its name can change if you change things about the schematic. So, if you apply a netclass to this net, you can accidentally drop it out of the netclass just by changing things about your schematic. This is why using net labels is important when using netclasses.

Thanks for the explanation. So, what should be the most reasonable workflow regarding netclasses in version 7?

The most reasonable workflow is to assign them in EEschema rather than in PCBNew. (This is a new feature in 7.0.)

See the schematic editor documentation for up-to-date netclass info for v7 (we haven’t updated the pcbnew netclass docs to match yet).

I realize that the schematic editor docs probably seem like a weird place for netclass documentation to live when you’re coming from v5/v6, but v7 adds a lot of features for assigning netclasses from the schematic, and the PCB editor netclass features are essentially a subset of the schematic editor netclass features.

I think using the schematic as the source of all info ievnet classes etc is the right way to go , really by the time you get to pcb 100% of the info should ideally be present

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Thanks for pointing this out. Indeed, this requires a new workflow compared to the older versions, but I totally see the rationale.

Thanks for the link!

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