As a relative noob to electronics and PCB designing I was happy to have become reasonably proficient in KiCad up to v6. All for very basic work. After a casual upgrade to v7, I find myself lost when it comes to the use of netclasses. That part was really intuitive in v6, with all nets showing up in the netclasses section of the Board setup in PCB Editor. Assigning net classes to the individual nets was easy.
Unfortunately this doesn’t clear things up for me. I do not begin to understand how to work with netclasses. One of the nets in my schematic is easily assigned a netclass by right-clicking and then choosing “Assign netclass…”. But the others cause a pop-up that says the net must be labeled first.
How is that an improvement? Do I now have to manually name or label each net on my PCB before I can assign a netclass? This was entirely automated in v6 and very easy to use. The post referred to above explains that there are reasons for abandoning the “anonymous net names”. (A net can’t be anonymous if it has a name, even if automatically generated…) But that reason is beyond my simple use of KiCad with which I never ran into problems or “instability” of “anonymous” nets.
Is there a resource that explains the new way of working with nets and net classes for simpletons like me? The documentation for v7 doesn’t help me get a grip on this. Please help. I need a workable workflow…
Patterns: this is what you describe in your post. You can do this in the net class setup dialog or by right clicking a (named) net and selecting assign net class, which has the effect of creating a pattern for that specific net.
Graphically: in the schematic, you can add a netclass directive to individual nets with a button on the right toolbar. This is like a label but assigns a netclass instead of a net name. These work on both named (labeled) and unnamed (unlabeled) nets. In addition to netclass directives, you can now add netclass assignments in regular labels by adding a netclass field to the label (label fields are new in v7).
As an example which may help illustrate, I use a mix of these features. For power nets, I use the patterns so I can do something like GND* to assign all of my grounds to a single power netclass automatically. For signal nets, I use netclass directives for all my unlabeled nets, and for nets that are labeled I just add a netclass field to the label.
There a few things I think could be improved with the new system (the pattern dialog needs some up/down arrows to rearrange the pattern priority, and I miss having a list of all of the nets in the design and their respective netclasses in one place) but the benefit of this is that in v7 you can assign netclasses to nets that aren’t labeled. You could sort of do it in v6, but it was fragile and broke whenever your net names changed. The graphical assignment is also just really convenient.
The point of the new approach is starting to dawn on me. And come to think of it, I have been surprised by changes in “anonymous” net names. Looks like KiCad became an even better better tool for people who know what they’re doing. For me, it requires me to understand the circuits that I’m working on better. Not necessarily a bad thing…
Can someone please give some guidance on the use of net class directives vs net labels? The easiest way I see is to label nets. In what kind of use case would net class directives be useful compared to net labels?
If you are at electronic level you describe yourself I wonder what for you need net classes at all. Do you really need them or just use because they are? If you don’t need them then don’t use.
Except default net class I define only one class (HV) to put there nets that are ‘hi voltage’ (=24V) and specify higher clerance for them. At PCBs where the max voltage is 12V all my nets are in default class.
Not all VCC tracks have to be wider. To connect 4k7 pull-ups I use my standard 0.25mm, when I go with VCC under 0603 I use 0.4mm, when I went with it under TQFP I use 0.7mm (at corners) and 1mm for longer distances and under TQFP. So using so many widths I just left decision for each track and not use net class to set it.
I always have full bottom side filled GND so I practically have no GND tracks except connecting pads to vias being just next to them.
In addition to what craftyjon said, there are lots of nets that aren’t really important outside of the circuit and I don’t want to think of a name for, and for those you can just stick a netclass directive on.
For your inputs and outputs and other nodes with obvious names, I’ll use a label with a netclass field (or maybe a netclass directive in addition to a label for the reasons craftyjon mentioned)
For nodes that I don’t want to think of a name for, netclass directives to the rescue.
After a weekend of playing around with it I see now the v7 way of assigning net classes is eminently sensible. It requires some more thought in the schematic, but improves the workflow in the pcb editor. The pre-v7 way suited me better as a novice, as I don’t really have enough baggage to properly understand the circuits I’m working on. I mostly use designs that are not my own. And understanding some basic electronics is a long way from understanding proper PCB design. The former can be picked up relatively easily, the latter not so much. The v7 changes are a good encouragement to work on that…
I think the new method to assign net classes is definitely functional.
To not weigh down the schematic sheet, I think an icon to toggle the display of the netclass directive label could be useful, like the icon to toggle the display of hidden pins in EEschema, which already exists.
In a dense schematic, adding further symbols, could confuse ideas, the netclass directive labels could be mistaken as power symbols or other
Let’s help each other to get this suggestion to the developers
Hi to all.
First I thought that the net class directive label aims that one can assign a net class to a segment (branch) of a net. It really does make sense in your example, when pullups connect to power despite the fact that it is useless to connect them with the same width as a power track requires. But when I assigned two different net class directive labels to the same net KiCAD threw an error. It turned out that this is the normal behaviour: "If more than one different netclass is graphically assigned to a single net, ERC will report an issue. " See https://docs.kicad.org/7.0/en/eeschema/eeschema.pdf
I am disappointed
It is impossible to transfer such information to PCB as routing of one net can have different structure than you have at schematic. If at schematic wire ends at pull-up resistor and you want to give it a separate netclass and then at PCB the track is going through that reistor pad to something else than what is the net-class of that tracks?
You probably can reach what you assumed using net-ties - one net is divided into logically two nets so you can assign each of them different net-class.