Vto is not V_GS(th) - but it's not defined in the documentation, it's assumed that the user know this


#1

“Zero-bias threshold voltage” (Vto) is not “Gate threshold voltage” VGS(th).

But the term “Zero-bias threshold voltage” is not defined in the documentation, so some users may think that it’s the same as the “Gate threshold voltage”.

But it’s not.



#2

Usually most analog engineer know about this. Other user many not event thinking about write pspice model for themselves.


#3

Sometimes is practical to get a spice model for a similar transistor and change the Vto (because it’s the main difference).


#4

May be that would be the last think I would do, if I can not find the model from the manufacture on that one. Finding Vto in the datasheet isn’t easy.


#5

The ngspice manual describes the existence of the VDMOS model in ngspice, a set of model equations relating currents or capacitances with terminal voltages for power transistors. To become alive, the model (equations) need a set of parameters. The required parameters are listed in the table cited above (together with some default values). The parameters typically have a physical background and enable a thorough description of the (measured) device behavior, when a suitable value for each parameter has been chosen.

The manual does not discuss reading data sheets. It is another, nevertheless interesting story how to translate data sheet values and graphs into VDMOS model parameter values. Ideally this should be the task of the device manufacturer, to deliver proper parameter data sets for each device offered. Today devices makers often deliver PSPICE compatible subcircuit models, but no VDMOS parameters for their devices. The VDMOS model was created by the LTSPICE developers, to simplify the device description and remove source of non-convergence.

If somebody is out there having a proven way of generating VDMOS model parameter values from device data sheets, I would be happy to learn about that.


#6

@Val
From reading Chapter 4 and Appendix B of Massobrio/Antognetti several times, I recall the only difference between V_th and V_t0 (when V_bs = 0) is the flatband voltage, V_fb, due to contact potentials in and around the MOS junction. SPICE Models were designed to accept parameters which can actually be measured practically. In a subsequent chapter of the book (Chapter 6), they go over techniques of how you can measure V_t0 and φ_p (inversion potential), which then the SPICE program can infer V_fb on its own (V_th can be written in terms of V_t0 and φ_p) instead of making the model author calculate that parameter explicitly.

If none of that makes sense, then that’s good too because @holger 's point is made crystal clear by this. This type of work should typically done by the device manufacturer. There is a vast amount of knowledge separating between SPICE model user and SPICE model author. If you’re going to delve into model authoring, including just tweaks, expect it to not be straightforward most of the time.

@holger
I don’t know if this has been proven and I never tried it, but there was a Windows tool for doing this. It’s mentioned in the older help file from LTspiceIV:

I found this program several years ago, but never ended up trying it out. I would attach it for you, but I don’t know what the policy is here on attaching .EXEs or ZIPs with them inside.

UPDATE: It’s available via a link on the 2nd post of this thread: https://stromrichter.org/showthread.php?tid=3996


#7

You can just measure it (roughly) empirically. Connect an ohmmetter (with low voltage) and change the gs voltage until the resistance stop to decrease.


#8

Hum… that work if I have part on my hand :slight_smile:


#9

I have got it.

Thanks


#10

Wait,

  • Vth = Vto when there is no body effect.
  • The VDMOS have Source and Body are shorted physically together.

So there should be no body effect at all. Why do we need to worry about the Vto not been difference from Vth? Datasheet turn on Gate Voltage have no thing to do with Vth or Vto.

I doubt that measuring the Rds_on method @Val suggested to me would work at all. When Vgs < Vth, the current in Drain conduct independently on Vds so it not behave like a resistance, but rather like a BJT. To estimate this, we have to play with Vds and Vgs until we got a curve Ids ~= exp(~Vgs) regardless Vds…


#11

Would this article help? https://www.researchgate.net/publication/235999817_A_new_SPICE_model_of_VDMOS_transistors_including_thermal_and_quasi-saturation_effects


#12

Some additional info here regarding V_t0 measurement. I scanned the relevant pages from the book I referenced above.
CCF01152019-rotated.pdf (1.7 MB)


#13

Vth is VGS required to strongly invert the surface of the substrate under the gate

gate to source voltage required to saturate the channel when the drain to source voltage is zero

According to my understanding this means that at the Vth the gate-source resistance is the lowest possible (for infinitely small currents and when the voltage between the base (a.k.a. body/bulk/substrate) and the source is 0). The resistance is the lowest possible when the channel is “saturated” (the surface is “strongly inverted”).

The VGS(th) is the voltage when the current starts to leak between the gate and the source (for example, when VDS = VGS, ID = 1 mA - in the datasheet of 2N7000).

The Vth (Vt0, Vto) is slightly larger (or much larger?) than the VGS(th).

Am I understanding it correctly?

I made a test simulation with:

.model 2N7002 VDMOS(Rg=3 Vto=1.6 Rd=0 Rs=.75 Rb=.14 Kp=.17 mtriode=1.25 Cgdmax=80p Cgdmin=12p Cgs=50p Cjo=50p Is=.04p mfg=Fairchild Vds=60 Ron=2 Qg=1.5n)

The result:

Vto=1.6
Vgs(th)@250uA≈1.65V

I expected the opposite. Why the Vgs(th) is bigger than the Vto?


#14

I don’t think you measure Vth in the right way. You cannot just pick any random current for measure Vth. Also, your circuit have Vd and Vg are interact which make the measurement if Vth is harder.


#15

I measure Vgs(th)@250uA (like in the datasheet):

The Vto is given in the .model, I don’t measure it.


Here I try to “measure” the Vto. I can’t use zero drain-source voltage, so I use 1 nV.

But the resistance is increasing up to 20V. Does this mean that Vto is over 20V? This do not make sense.

In the chart the current is not stopping to increase, therefore the surface of the substrate is not strongly inverted (the channel is not saturated).

This do not make sense.


#16

Remember, datasheet are selling data, and min, max and typical data from testing 100 or 1000 IC, and other practical issue that VDMOS along would not model completely physical device. The model usually provide are usually try to match “typical” data.
So to get model data, I usually have to use the graph/chart in the data sheet. And use method like @Ste suggested. I had never measure using simulation. But I can use another method to find Vth like I had suggested. So if you can introduce a just fast enough square wave on the Vd, and keep ramp up Vg from 0 to may be 2V. Base of the book model, I think you can find the Vg that show the current start to have a square wave from Vd. Vth should be some where there.


#17

The expected difference is about 1-2 volts, not over 20 volts.


#18

MOSFETs have subthreshold conduction which is caused by diffusion current in depletion areas and difficult to model alongside drift current in inversion areas. I don’t know how well the LTspice VDMOS structure models this. The BSIM models have special parameters to get better contributions of both types of currents. Therefore, using the model itself at low conduction to back-calculate and infer the V_t0 seems like a poor practice to me.


#19

Except - to verify the model and correctness of the simulation.


#20

Of course, this is the reason - I want to demonstrate that the simulation make sense (produce the expected results).

But I can’t. Maybe I don’t understand something. Or the simulation is very incorrect.

I expected that the resistance drain-source would stop to decrease at Vto, however this do not happen. The drain current (at constant drain-source voltage!) continue to increase when the gate-source voltage is increasing. The simulation stops at 20V gate-source voltage. This is way above the expected 1.6V

Maybe there are other factors leading to reduced resistance (after “saturation”)? But this do not make sense - using the term “saturation” in this way.

The channel is saturated at 1.6V, but not the transistor as a whole. Is this make sense?