Vto is not V_GS(th) - but it's not defined in the documentation, it's assumed that the user know this

Schematic Simulation (Ngspice)
21

Resistance R = Vds / Ids. This is extremely non-lieaner, so it is hard to use R for analyzing the model. Givent Vds always > ~Vt:

  • In turn off region: R is very large, and proportional to ~Vds/exp(Vgs)
  • In linear region: R is smallest, and proportional ~1/(Vgs-Vds)
  • In Saturation region: R is proportional to ~(Vds/100V)/Vgs^2

Again, calculate Vth, using the linear region is the most practical way. Or you can estimate by find the Vgs where Ids change from independent from Vds to depend on Vds. This is why I ask you to give Vds like a square wave between 5V and 10V. So that would help you to find the point where square wave show up in Ids.

But to verify model, you may need to plot the three theoretical curve and compare with the simulation result.

22

You can see the FET is turn on around 1.6V in your latest simulation, where the current start to conduct. That is when the current start to dependent on the Vds voltage.