It turns out this is just part of a bigger oversight on my part. I have some assembled SMT boards on their way back that are going straight into elec recycling because I used the symbol for the 2N3904 TO-92 and simply replaced the footprint with an SOT-23, having ASSUMEd the pin numbers would correspond. Ugh. Ugh ugh. I don’t know what else might be wrong in there but all the pick-and-place work is suspect.
Painful as that is, the price of writing off that work is peanuts compared to the time I would have spent tracking the problem down after getting everything wired up so I’m glad we had this discussion.
Going forward, I’m populating dedicated symbol and footprint libraries for JLC jobs. I’d already used a bit of Perl to implement the approach described here as a means of importing symbols for all the passives: Autogenerated kicad libraries for jlcpcb assembly.
If I can get this working at all I’ll probably be elated enough to start another thread to boast about it. Hope that’s OK. Thanks for the support and next time I’ll be sure to do more searching up front.
I guess these were intended for sale, in which case I’m sorry for your financial loss. If they’re just prototypes you can rescue them by either twisting or dead bugging the part to fit the incorrect footprint. I know this because I’ve done it more than once unfortunately.
I gently suggest you take a deep breath and count to 10. As you seem new to this, don’t go on a long and difficult route.
I have JLC assemble pcb routinely.
Export the fab data for the desired side.
Rearrange and rename the colums per JLC spec.
Upload.
Check part orientation visually. Update csv file, re-upload.
It really isn’t that difficult.
No changes to libs. You’ll learn which devices are wrong initially and can often make the correction before the first upload.
I had working in some fixes for a Pcbnew JLCPCB plugin for v5.99/v6
That make the work of converting the position files.
Basically, KiCad uses a “A” and JLCPCB a “B” variation of the standard of SMD position (if someone search, it is mentioned in a past thread about JLCPCB). They basically change which quadrant the pin 1 should be in the library drawing for each package format.
Change library is a bad approach, since the KiCad library is well checked for the library manteiners and community, and the conversion A<>B standard is straight forward (see the plugin have a file with this conversion).
I also used the same plugin pointed by @diegoherranz in a past layout, it use the generated files output from Pbcnew as input.
The plugin that I posted on the other thread appear direct on Pcbnew, removing some intermediary steps that may induce mistakes (and use the same rotation logic).
I don’t understand why people think rotations are so hard with JLCPCB. You get the preview, change the CPL file rotations to fix any problems and reupload it. Takes a few minutes.
It helps to have a pin 1 indicator on the silkscreen. For polarized 2 pin components, a + on the SS is helpful, too.
I suppose having the correct rotation figured out automatically would be good but I am always going to verify that their interpretation of my gerbers/bom/cpl is the same as mine.
Hard, it is don’t. (sounds like Yoda…) And check it is always a good procedure.
But avoiding make this procedure by hand will avoid mistaken/forgetfulness. If I remember, also polarized SMD capacitors follow the other notation (180° on KiCad vs JLCPCB position files comment above), and in high populated PCBs the change of forgot one single component increase.
The plugins and scripts that KiCad users created are an automatized way to do and, footprints not correct rotated by them can be easy fix on the code.
Clearly there’s more than one way to do this and different solutions work for different people. The fact that KiCad is flexible in this way is a Good Thing.
As for myself, I am very sloppy by nature(*) so relying on visual inspection+correction is not going to work for me. I want to be able to place a part on a schematic and have the BOM and the footprints be correct, period. As I understand it, the way to achieve this goal is to build libraries of atomic parts (if that’s the right term) with footprints (including extra dots as appropriate) that will be properly handled by JLC’s assembly. Since my designs generally rely on a small selection of parts (TL072/4 and LM13700 account for over 90% of the chip count) I expect the ramp-up to be pretty quick.
At the same time, I look forward to visually inspecting everything before pulling the trigger on production, now that I know what to look for. If this approach doesn’t work out, maybe I’ll have the guts to come back and explain where I was wrong.
Thanks to everyone for your input, the engaged and opinionated community here is a real asset.
(*) I ditched EE for software many moons ago mostly because in software your mistakes don’t destroy your components. Now I’m trying to find my way back.
There are two standards for placement according to IPC7351, A and B. You can download a copy of the specification document from www.pcblibraries.com (You do have to register).
I had a friend who got a job writing software for industrial controllers. To debug his code he started stepping through it. He stopped to examine one line that allowed for a fairly large capacitor to charge. The software destroyed a component in a quite dramatic fashion.
I absolutely apreciate those standards. Sad to say, that in real life moste people either dont care about them, or dont know they exist. So its the normal daywok of every ems company to correct those XY placement data files for every job (at least you have to correct it once per customer and footprint, and your software will recognize it the next time the same customer orders).
So In my opinion, this is no JLC problem, its a general problem, but maybe its often the first time for kicad users to order populated pcbs at all.
Buy locally in countrys were someone cares for human rights, maybe also eleminates this problem
Well, the rotations are not hard until you encounter some problematic parts. I’ve covered this in another post allready ( JLC Component Position Offset ) but TLDR; is that if you have a component, that does have mark on pin 3 (instead of pin 1) then it is a lottery how it will come up. And no matter how much you use the web placement viewer, mark 1 and notch on silkscreen. email with the support, send them screenshot from KiCad… I did even order the test board just to see whether the component will be ok and next time they rotated it differently
Yeah, the upshot in that thread is that you really do need to indicate on the silk screen layer how the part goes if there is any ambiguity. Fortunately, this is fairly rare. But in general, the more info you force them to see (ie on the SS layer), the higher the chances of them getting it right.
I have done a number of designs through JLCs assembly service and even identical runs (same Gerber, BOM and CPL files) have different problems that they point out. You just have to work your way through them.
If there wasn’t the real possibility of wasting money and a couple of weeks on a board run, the language barrier would be fairly humorous.
Well, you can see in the linked post that I marked on silk screen:
Pin 1
Pin 3
Notch
and still I’ve got mixed results. But this is really unfortunate case as similar LED has notch on pin 1…
But to be fair also in PCBWAY they positioned the LEDs incorrectly but as they do send pictures of finished assembly, I was able to ask them to rotate the LEDs correctly. And the problem was mostly on my side because in that version I had moved most of the information from silkscreen to fabrication layer and I’ve added the fabrication PDF only into gerbers and not into PCBA files…
