JLCPCB BOM and Pick and Place

I am interested in exploring how my KiCAD designs SMT could be fabricated by the new JLCPCB service.

I have finally wrapped my head around the very convoluted and non intuitive BOM process KiCAD has, not sure that the final BOM format is suitable for JLCPCB?

Is there anyway to generate a pick and place file that would be suitable for JLCPCB?

Anyone here been successful with interfacing with JLCPCB SMT fab service?

I don’t know about JLPCB but I’ve had many KiCad-designed boards assembled by pcbway. You just send them gerbers, the drill file, the .pos files and the .csv BOM file. Works great!

It isn’t perfect, see the twitter thread here for some more info: https://twitter.com/FauthNiklas/status/1158106370186649600

Thank you for sending this…

Thanks for the input to date…I am still following the JLCPCB path at the moment and all was going swimmingly well until I uploard the CPL (.pos) file. They allow you to check the position of components before proceeding to order.

All the passive resistors and capacitor positions are fine, diodes fine however all the ICs, regulators are all missed placed? No common denominator some are 90, some 180 and some are 270 out.

I can manually go in and correct these positions but wondering why only these type of components are wrong and they all are.

Anyone else had the same issue?

I am using KiCad 5.0.0

Cheers…

Hello: Today I tried to upload a pcb design and I encounter the same problem. R, C and D is correctly placed. But ICs and transistors are rotated as you mention, some 90 and another 180 degrees.
Send a query to JLCPCB.
You could solve it?

It appears that JLC is mostly using the EIA standard for orientation. EIA seems to be the most widely used in the industry, which is unfortunate because it isn’t predictable or consistent. The orientation changes depending on the part type e.g. tantalum caps have a different polarity than diodes.

KiCad libraries appear to use the IPC standards, which consistently put pin 1 in the upper left quadrant or on the left for two pin parts.

Ref: EIA-481-D standard, IEC61188 standard, IPC-7x51 standards.

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I stumbled upon the same problem and got in touch with the JLCPCB helpdesk about it. This is what they replied:

Sorry for the inconvenience caused on preview.

Normally, the preview just for the reference and some won’t shown and the orientation is not correct, while we will send you manually DFM before proceed if you have written the memo down on note section.

Now, how do we want to interpret that? Will they send me something (what exactly?) for a final confirmation from me that everything is correct before starting production?

I have the same question. The 3D visualization used by them preview all the passives (and bipolar semiconductors) as one resistors. It not obvious to see if the diodes (LEDs) are correct (Are they always correct, @Fleetz? ).

If all IC, regulator, transistors (in my case) are inverted, is simple add a conditional situation at NiklasFauth script.

Actually diodes are pretty well marked, in my case at least. They even look correctly oriented, even though it seems the latest Kicad footprints have made every effort to be as hard to decode as possible.

Calculate how many degrees the device is out and modify the position file, then check out the modified file using the JLCPCB online viewer/checker. Wasn’t too hard to get it correct.
Now have a couple of board which are now loaded fine using their fab service…

A reference document

so manually changing the file and using there visual tool is the best way to go about it? i am bit hesistant to do that since they say its only for reference

Can’t think of an easier way. It’s only a xcel file. When I sent the file up to JCLPCB it shows you the position of the components. I simply calculated what the correct position should be changed the value saved the file and resent up to JCLPCB and checked the position again on their viewer. Maybe one day KiCAD might give you the option to choose between the various position standard…in the meantime this is my work around.

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The https://github.com/matthewlai/JLCKicadTools @matthewlai script appear to check each case.

While that script is better than the manual approach (which is what I ended up doing for my JLCPCB order, after trying a bunch of things), I don’t believe that package-name-based adjustment is the fully-correct general solution.

Look at my previous post referencing the EIA-481-D standard, IEC61188 standard, and IPC-7x51 standards. With EIA the rotation correction depends on the part function, not just the part shape.

IF the ad hoc script does become the common approach, it’s going to need quite a bit more work extending the tiny correction list. And even with that database, it’s eventually going to need a way to move per-component rotation correction from the schematic into pcbnew, preferably in a way that changing the footprint is likely to work correctly.

On a related point, this does make it obvious that the default footprint orientation indications aren’t especially clear.

Yes. Should be possible to choose between those standards file output at the position file output dialog of pcbnew.

That certainly would be nice if that were to be done.

KiCad would then need to know the zero position that every footprint was designed in.

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Right now KiCad (really, the default footprints) does appear to follow the IPC standard. Pin 1 is in the upper left quadrant, or on the left for on-axis parts.

That is a reasonable choice, perhaps the only reasonable choice when the part type is chosen separately from the footprint.

But it suggests that an additional piece of information, orientation, needs to be included in the netlist so that the part selection in schematic capture can be communicate the tape/reel/tray orientation to pcbnew. With consideration for parts that can be ordered with more than one packaging orientation e.g. with a part number suffix.

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