I am dipping a toe into the SMT assembly waters with JLCPCB’s service. Attached are a PCBNew file for a board with a single SMT part and the .pos file I generated from File->Fab->Footprint Position.
Comparing the top-pos.csv with the PCB layout, it looks mostly right and fairly simple: the only discrepancy is that the Y coordinate is negative in the .csv. (I can sort of see that, the orientation of the Y axis in PCBNew has always seemed unnatural to me, but whatever, I can deal.)
Having uploaded the job to JLC, I can see (in “DFM analysis”) where they have the part jammed into the lower right corner of the board with the rotation off by 90 (or 270 degrees). They repositioned it correctly.
I included another more ambitious board in the same job, with 3 ICs and a couple dozen smaller parts. The resistors, diodes, transistors all got placed perfectly. So did the ICs, but their rotation was off 90 degrees. (These three errors also got corrected.) I’ve not included those files here so we can focus on the simpler case.
I’ve asked JLC about it and want to raise it here so as to be sure I’m generating the files properly.
Is there some way to graphically view the instructions of the footprint position file? It seems like this would be a natural feature for the Gerber viewer but the only thing I could think of was to include the pos.csv in the .zip file and GerbView flagged it as unrecognizable.
Comments on the board design in general are also welcome. It’s a (bipolar) control voltage display for use in modular analog synths so there should be nothing at all finicky about the signal paths.
I used this VisualPlace for precisely this case, it was however a one shot and I am unable to offer much guidance.
You don’t state your kicad version but on the stable version (>5.1.7) you can now choose if you want the back side negative or positive for the X axis.
KiCad already has a 3D viewer, and I don’t think that adding another 3D viewer that interprets placement data would help much. That placement data is generated from the information already in KiCad, so it would just re interpret the same data.
The underlying problems are (possible) bugs in rotation of 3D models, or more likely, adhering to different “standards”.
This can not be solved by adding another 3D viewer to KiCad. What you need is a 3D viewer that interprets the data in the same way as your assembler does.
It is my understanding that rotation of the part depends upon the initial orientation of the part in the pocket of the reel. For an SOIC part, the standard is typically to have the number 1 pin in the upper left corner. A rotation of 180 degrees appears to me to be correct for your rotation.
It is also my understanding that auxiliary origin needs to be placed to provide a reference for the position file.
A couple of interweb searches have indicated that the lower left corner of the board is typically the standard.
I have not yet sent out a board for population. When using KiCad, hitting the space bar over this auxiliary origin will set PcbNew to 0,0 on the DX and DY indications. Placing the cursor over the anchor point of U1 will result in the same numbers indicated as are generated by the fabrication output position file.
Would appreciate any feedback on what you find to actually work with JLCPCB.
Google for “kicad jlcpcb assembly” and you’ll find some tutorials/plugins. JLC also has their own viewer for the placement data. But it’s all buggy, so they have humans going over submissions and will contact you if they think there are errors, don’t sweat it too much. Do put some effort into making your silkscreen informative however (designators readable and next to their components, clear pin1/polarity markings.
considering their audience, there’s really not an alternative. if they tried to make it fully automated, 90% of their customers would ■■■■ up and cause a support nightmare.
@gvcastellano And that thread mentioned nothing about the auxiliary origin placement…
Place the auxiliary origin marker on the bottom left corner of your pcb edge cuts line and run the Fabrication Outputs/Component placement tool. Then compare your new results with JLCPCB.
U1 is a TL074, LCSC C6963. I just thought to bring up the EasyEDA footprint linked to that ID and it’s rotated 90/270 relative to what’s in “our” footprint library.
It turns out this is just part of a bigger oversight on my part. I have some assembled SMT boards on their way back that are going straight into elec recycling because I used the symbol for the 2N3904 TO-92 and simply replaced the footprint with an SOT-23, having ASSUMEd the pin numbers would correspond. Ugh. Ugh ugh. I don’t know what else might be wrong in there but all the pick-and-place work is suspect.
Painful as that is, the price of writing off that work is peanuts compared to the time I would have spent tracking the problem down after getting everything wired up so I’m glad we had this discussion.
Going forward, I’m populating dedicated symbol and footprint libraries for JLC jobs. I’d already used a bit of Perl to implement the approach described here as a means of importing symbols for all the passives: Autogenerated kicad libraries for jlcpcb assembly.
If I can get this working at all I’ll probably be elated enough to start another thread to boast about it. Hope that’s OK. Thanks for the support and next time I’ll be sure to do more searching up front.
I guess these were intended for sale, in which case I’m sorry for your financial loss. If they’re just prototypes you can rescue them by either twisting or dead bugging the part to fit the incorrect footprint. I know this because I’ve done it more than once unfortunately.
I gently suggest you take a deep breath and count to 10. As you seem new to this, don’t go on a long and difficult route.
I have JLC assemble pcb routinely.
Export the fab data for the desired side.
Rearrange and rename the colums per JLC spec.
Upload.
Check part orientation visually. Update csv file, re-upload.
It really isn’t that difficult.
No changes to libs. You’ll learn which devices are wrong initially and can often make the correction before the first upload.
I had working in some fixes for a Pcbnew JLCPCB plugin for v5.99/v6
That make the work of converting the position files.
Basically, KiCad uses a “A” and JLCPCB a “B” variation of the standard of SMD position (if someone search, it is mentioned in a past thread about JLCPCB). They basically change which quadrant the pin 1 should be in the library drawing for each package format.
Change library is a bad approach, since the KiCad library is well checked for the library manteiners and community, and the conversion A<>B standard is straight forward (see the plugin have a file with this conversion).
I also used the same plugin pointed by @diegoherranz in a past layout, it use the generated files output from Pbcnew as input.
The plugin that I posted on the other thread appear direct on Pcbnew, removing some intermediary steps that may induce mistakes (and use the same rotation logic).
I don’t understand why people think rotations are so hard with JLCPCB. You get the preview, change the CPL file rotations to fix any problems and reupload it. Takes a few minutes.
It helps to have a pin 1 indicator on the silkscreen. For polarized 2 pin components, a + on the SS is helpful, too.
I suppose having the correct rotation figured out automatically would be good but I am always going to verify that their interpretation of my gerbers/bom/cpl is the same as mine.
Hard, it is don’t. (sounds like Yoda…) And check it is always a good procedure.
But avoiding make this procedure by hand will avoid mistaken/forgetfulness. If I remember, also polarized SMD capacitors follow the other notation (180° on KiCad vs JLCPCB position files comment above), and in high populated PCBs the change of forgot one single component increase.
The plugins and scripts that KiCad users created are an automatized way to do and, footprints not correct rotated by them can be easy fix on the code.
Clearly there’s more than one way to do this and different solutions work for different people. The fact that KiCad is flexible in this way is a Good Thing.
As for myself, I am very sloppy by nature(*) so relying on visual inspection+correction is not going to work for me. I want to be able to place a part on a schematic and have the BOM and the footprints be correct, period. As I understand it, the way to achieve this goal is to build libraries of atomic parts (if that’s the right term) with footprints (including extra dots as appropriate) that will be properly handled by JLC’s assembly. Since my designs generally rely on a small selection of parts (TL072/4 and LM13700 account for over 90% of the chip count) I expect the ramp-up to be pretty quick.
At the same time, I look forward to visually inspecting everything before pulling the trigger on production, now that I know what to look for. If this approach doesn’t work out, maybe I’ll have the guts to come back and explain where I was wrong.
Thanks to everyone for your input, the engaged and opinionated community here is a real asset.
(*) I ditched EE for software many moons ago mostly because in software your mistakes don’t destroy your components. Now I’m trying to find my way back.
