Understanding the footprint position file--reworked by JLCPCB

There are two standards for placement according to IPC7351, A and B. You can download a copy of the specification document from www.pcblibraries.com (You do have to register).

I had a friend who got a job writing software for industrial controllers. To debug his code he started stepping through it. He stopped to examine one line that allowed for a fairly large capacitor to charge. The software destroyed a component in a quite dramatic fashion.

I absolutely apreciate those standards. Sad to say, that in real life moste people either dont care about them, or dont know they exist. So its the normal daywok of every ems company to correct those XY placement data files for every job (at least you have to correct it once per customer and footprint, and your software will recognize it the next time the same customer orders).
So In my opinion, this is no JLC problem, its a general problem, but maybe its often the first time for kicad users to order populated pcbs at all.
Buy locally in countrys were someone cares for human rights, maybe also eleminates this problem :stuck_out_tongue:

A Feranec call about this standard (1h46m45s).

Well, the rotations are not hard until you encounter some problematic parts. I’ve covered this in another post allready ( JLC Component Position Offset ) but TLDR; is that if you have a component, that does have mark on pin 3 (instead of pin 1) then it is a lottery how it will come up. And no matter how much you use the web placement viewer, mark 1 and notch on silkscreen. email with the support, send them screenshot from KiCad… I did even order the test board just to see whether the component will be ok and next time they rotated it differently :slight_smile:

Yeah, the upshot in that thread is that you really do need to indicate on the silk screen layer how the part goes if there is any ambiguity. Fortunately, this is fairly rare. But in general, the more info you force them to see (ie on the SS layer), the higher the chances of them getting it right.

I have done a number of designs through JLCs assembly service and even identical runs (same Gerber, BOM and CPL files) have different problems that they point out. You just have to work your way through them.

If there wasn’t the real possibility of wasting money and a couple of weeks on a board run, the language barrier would be fairly humorous.

Well, you can see in the linked post that I marked on silk screen:

  • Pin 1
  • Pin 3
  • Notch
    and still I’ve got mixed results. But this is really unfortunate case as similar LED has notch on pin 1…
    But to be fair also in PCBWAY they positioned the LEDs incorrectly but as they do send pictures of finished assembly, I was able to ask them to rotate the LEDs correctly. And the problem was mostly on my side because in that version I had moved most of the information from silkscreen to fabrication layer and I’ve added the fabrication PDF only into gerbers and not into PCBA files…

… see “Commodore PET killer POKE”… :wink:

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