Google for “kicad jlcpcb assembly” and you’ll find some tutorials/plugins. JLC also has their own viewer for the placement data. But it’s all buggy, so they have humans going over submissions and will contact you if they think there are errors, don’t sweat it too much. Do put some effort into making your silkscreen informative however (designators readable and next to their components, clear pin1/polarity markings.
Wow, ok, I didn’t do my research up front, this has been covered in JLCPCB BOM and Pick and Place. Plenty to chew on there.
Surprising how much human intervention is involved in that operation, considering their pricing.
considering their audience, there’s really not an alternative. if they tried to make it fully automated, 90% of their customers would ■■■■ up and cause a support nightmare.
@gvcastellano And that thread mentioned nothing about the auxiliary origin placement…
Place the auxiliary origin marker on the bottom left corner of your pcb edge cuts line and run the Fabrication Outputs/Component placement tool. Then compare your new results with JLCPCB.
BTW, would mind sharing the part number of U1?
U1 is a TL074, LCSC C6963. I just thought to bring up the EasyEDA footprint linked to that ID and it’s rotated 90/270 relative to what’s in “our” footprint library.
It turns out this is just part of a bigger oversight on my part. I have some assembled SMT boards on their way back that are going straight into elec recycling because I used the symbol for the 2N3904 TO-92 and simply replaced the footprint with an SOT-23, having ASSUMEd the pin numbers would correspond. Ugh. Ugh ugh. I don’t know what else might be wrong in there but all the pick-and-place work is suspect.
Painful as that is, the price of writing off that work is peanuts compared to the time I would have spent tracking the problem down after getting everything wired up so I’m glad we had this discussion.
Going forward, I’m populating dedicated symbol and footprint libraries for JLC jobs. I’d already used a bit of Perl to implement the approach described here as a means of importing symbols for all the passives: Autogenerated kicad libraries for jlcpcb assembly.
If I can get this working at all I’ll probably be elated enough to start another thread to boast about it. Hope that’s OK. Thanks for the support and next time I’ll be sure to do more searching up front.
I guess these were intended for sale, in which case I’m sorry for your financial loss. If they’re just prototypes you can rescue them by either twisting or dead bugging the part to fit the incorrect footprint. I know this because I’ve done it more than once unfortunately.
I hate throwing stuff away so I might try some kind of salvage. I guess it’s time to spring for a pair of SMT tweezers.
They’re supposed to be working prototypes–ADSRs for analog synthesis.
I gently suggest you take a deep breath and count to 10. As you seem new to this, don’t go on a long and difficult route.
I have JLC assemble pcb routinely.
- Export the fab data for the desired side.
- Rearrange and rename the colums per JLC spec.
- Upload.
- Check part orientation visually. Update csv file, re-upload.
It really isn’t that difficult.
No changes to libs. You’ll learn which devices are wrong initially and can often make the correction before the first upload.
I had working in some fixes for a Pcbnew JLCPCB plugin for v5.99/v6
That make the work of converting the position files.
Basically, KiCad uses a “A” and JLCPCB a “B” variation of the standard of SMD position (if someone search, it is mentioned in a past thread about JLCPCB). They basically change which quadrant the pin 1 should be in the library drawing for each package format.
Change library is a bad approach, since the KiCad library is well checked for the library manteiners and community, and the conversion A<>B standard is straight forward (see the plugin have a file with this conversion).
I have used https://github.com/matthewlai/JLCKicadTools successfully to prepare the BOM and pick and place files for JLCPCB. I would recommend to give it a try.
I also used the same plugin pointed by @diegoherranz in a past layout, it use the generated files output from Pbcnew as input.
The plugin that I posted on the other thread appear direct on Pcbnew, removing some intermediary steps that may induce mistakes (and use the same rotation logic).
I don’t understand why people think rotations are so hard with JLCPCB. You get the preview, change the CPL file rotations to fix any problems and reupload it. Takes a few minutes.
It helps to have a pin 1 indicator on the silkscreen. For polarized 2 pin components, a + on the SS is helpful, too.
I suppose having the correct rotation figured out automatically would be good but I am always going to verify that their interpretation of my gerbers/bom/cpl is the same as mine.
Hard, it is don’t. (sounds like Yoda…) And check it is always a good procedure.
But avoiding make this procedure by hand will avoid mistaken/forgetfulness. If I remember, also polarized SMD capacitors follow the other notation (180° on KiCad vs JLCPCB position files comment above), and in high populated PCBs the change of forgot one single component increase.
The plugins and scripts that KiCad users created are an automatized way to do and, footprints not correct rotated by them can be easy fix on the code.
Clearly there’s more than one way to do this and different solutions work for different people. The fact that KiCad is flexible in this way is a Good Thing.
As for myself, I am very sloppy by nature(*) so relying on visual inspection+correction is not going to work for me. I want to be able to place a part on a schematic and have the BOM and the footprints be correct, period. As I understand it, the way to achieve this goal is to build libraries of atomic parts (if that’s the right term) with footprints (including extra dots as appropriate) that will be properly handled by JLC’s assembly. Since my designs generally rely on a small selection of parts (TL072/4 and LM13700 account for over 90% of the chip count) I expect the ramp-up to be pretty quick.
At the same time, I look forward to visually inspecting everything before pulling the trigger on production, now that I know what to look for. If this approach doesn’t work out, maybe I’ll have the guts to come back and explain where I was wrong.
Thanks to everyone for your input, the engaged and opinionated community here is a real asset.
(*) I ditched EE for software many moons ago mostly because in software your mistakes don’t destroy your components. Now I’m trying to find my way back.
Back in my college days I knew some people who would take this as a challenge. 
There are two standards for placement according to IPC7351, A and B. You can download a copy of the specification document from www.pcblibraries.com (You do have to register).
I had a friend who got a job writing software for industrial controllers. To debug his code he started stepping through it. He stopped to examine one line that allowed for a fairly large capacitor to charge. The software destroyed a component in a quite dramatic fashion.
I absolutely apreciate those standards. Sad to say, that in real life moste people either dont care about them, or dont know they exist. So its the normal daywok of every ems company to correct those XY placement data files for every job (at least you have to correct it once per customer and footprint, and your software will recognize it the next time the same customer orders).
So In my opinion, this is no JLC problem, its a general problem, but maybe its often the first time for kicad users to order populated pcbs at all.
Buy locally in countrys were someone cares for human rights, maybe also eleminates this problem 
A Feranec call about this standard (1h46m45s).
