Track will not pass between pads as expected

Hi Community,

I’m trying to connect the two nodes circled in red ink, please see below;

It seems as though it should be a simple matter of threading my 10mils track (with 5 mils. clearance) between the 1mm pitched pads of the BGA. This poses no problem in the vertical direction (please see below);
But when I try to thread it through in the southerly direction between pads H8 and J8, KiCad prevents me from doing so … it behaves as if pad H8 has some additional (seemingly hidden) clearance requirements … forcing the track as close to J8 as is permissible (based on the expected clearance). Please see below;
That kink in the track (above) is as a result of some “hidden force” between H8 and the track, preventing the track from getting any closer to H8. In an attempt to understand, I switched to an alternate signal layer … and when I did, no problem threading the pads.

My best explanation was that pad “H8” has some weird/hidden parameters associated with it, relating to clearance … but if it does, I cannot seem to find them.

Any thoughts would be appreciated.

Many thanks,

Use “Highlight collisions” in your routing preferences to see where the conflict is.

@Seth_h … thank you, I didn’t know how to enable “Highlighting Collisions” … but as I poked around in an attempt to find that, I stumbled across Preferences->Legacy Toolset … when I selected this, the canvas changed, whereupon I was able to thread the track (as expected), I then switched back to the default “Modern Toolset” … and KiCad didn’t complain … so everything is OK, I guess … per picture below;

That said, if you can tell me how to enable “Highlighting Collisions” … I’d appreciate it, as that sounds handy for another time. I’m using KiCad 5, I should have mentioned that from the outset.

Many thanks,

When you start your router, right-click and choose the preferences at the bottom of the context menu. Default hotkey is Ctrl-,

Except still don’t know what was the reason of problem.

Thanks @Seth_h, I’m sorry, I wasn’t able to follow along. Also, I tried “Preferences->Hotkey Options” but I wasn’t able to find CTRL- (in the list) and when I pressed this, nothing seemed to happen. Not to worry, thanks for your help.

Exactly @Piotr … I find that it happens every now and then with no seemingly predictable pattern. In the past, shutting down the layout editor and restarting it seems to fix it or if not, shutting down KiCad and restarting … except in the case where neither of these worked and I took to the forum, above. If I ever discover the pattern I’ll find out how to submit a bug report and submit one. Cheers.

@Seth_h … Arrrrh … Got it ! Thanks so much. Tim.

I’ve hit a similar issue … and setting Route–>Interactive Router Settings to “highlight collisions” appears to point to the issue (though I cannot explain it). In the screen shot below, it should be possible to place my via (18 mils ring with 10 mils hole) equidistant between each of the four FPGA pads (design rule clearance 5 mils) because it doesn’t violate any rules that I know to and besides, I’ve placed plenty just like this, already. Please see screen shot, below;

Once an attempt is made to place the via at this position, the via is forced to the left of the white cross hairs (desired location) … please see screen shot below;
implying a violation to the right (of the via) … routing mode is set to “walk-around” in the above picture. When I switch to “highlight collisions” per @Seth_h, the issue appears to be with the track connecting K7 and K8? Please see below;

which I’m struggling to understand … it appears to me that KiCad might be “triple-counting” the required clearance? The 5 mils clearance around the via is fair enough (because this is consistent with what I have set-up in the design rules), but it appears that KiCad is also adding 10 mills of clearance around the 10 mill trace connecting K7 to K8? When I change the K7 to K8 track thickness to 5 mils the via is pushed over to the left (as before) but to a lesser degree, per screenshot below;

And with “highlight collisions” turned on, a similar situation as before but with what looks like the FPGA pads now dominating the collision (now that the K7 to K8 trace is 5 mils). Please see below;

Any further thoughts would be appreciated.

Many thanks,

If you’d like to share your board file, I might be able to point to whether it is a bug or configuration issue. Alternatively, you can check the “Allow DRC violations” in the routing settings, place the via and then run your DRC check to see more details about the two items that are colliding and their computed distances.

I found out that collision detection in the router does not handle floating point math quite well, there must be an epsilon missing in comparison somewhere.
I had an issue with 48 lqfp footprint, 0.5mm pitch, 0.3mm wide pads so there was exactly 0.2mm space between them. I tried to route 0.3mm wide tracks to those pads. I was able to route 46 out of 48 just fine but the remaining two just wouldn’t connect. I couldn’t even extend the track out of the pad at all, it was blocked completely.
As soon as I made my net clearance 0.199mm instead of 0.2mm everything worked. It was a footprint from official v5 library, angled at 45 degrees.

I don’t know if this will help OP but now I always put clearance as slightly less than what I actually want it to be so that it’s not noticeable in practice but KiCad doesn’t randomly turn into a stubborn goat that doesn’t want to step onto a shadow of itself.


Thanks @qu1ck … I relaxed the clearance but it did not help in this case. But I will keep this in my back pocket because what you described happened to me on this very board, to fix, I think I recall choosing an ever smaller grid to workaround it. Tim.

Thanks @Seth_h, I allowed violations, placed the via and then ran the DRC as you suggested, but it did not report any issues for that node. I played around to see it I could tease-out a little more information about what may be causing the violation as reported in the layout GUI vs. the DRC and in the picture below, I did not place a via, I simply attempted to thread a 5 mil trace … it looks like the collision detection is imagining a 10 mil clearance around the BGA pad?

Thanks for offering to take a look at the board file, please find attached.
xc7aXXtftg256.kicad_pcb (588.5 KB)

Thanks, I’ll take a look and make sure that there isn’t a mistake in the code.

As a heads up, the DRC check that you run is slow, thorough and accurate. The router DRC check is fast, errs on the side of caution and can be less accurate. If you depend on having exactly 0nm of clearance, you may run into these corner cases.

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Hey Seth, I’ll also have a look.


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@tholm: which version of Kicad do you have? Can’t reproduce it with ~3 days old nightly…

My guess is it is a grid problem.
The via is not in the centre of J8-K8-J9-K9

The easy way is placing the BGA at a better position. As this is not possible because a lot of routing is already done… though I would redo all the routing into the BGA to match the grid.

Follow this steps:

  1. Set the origin point of the grid on any pad of the BGA, for example K8
    View->grid settings Grid origin 121.7196 , 134.0208 in mm.
  2. Set the grid to either 0.5mm or 0.25mm
  3. Route the bga.

Your guess is wrong, it’s not a grid problem because the router in KiCad doesn’t rely on grid…


Are you sure about that? At least to me it feels like kicad is trying to place vias and trace end points to the grid if possible. (Even when using the interactive router)
Maybe this clashes with what DRC would suggest in some edge cases.