While run my simulation I get
TRAN: Timestep too small; time = 0,000545902, timestep = 1,25e-15: trouble with node “c4:power” run simulation(s) aborted
I could not find “c4:power” in netlist.
Would you be so kind to me as to point out to what I should read to resolve such things. Or better of, if you provide such courses.
power-pc-board.7z (15.7 KB)
Any luck with this so far?
I have not used NgSpice but I was doing a lot with LTSpice a while ago. Usually a good simulation will run at microseconds per second or faster, nSec per step or more. Is there any ability to choose solvers or trapezoidal versus modified trapezoidal integration?
One thing from another thread…be sure to update to the latest version. Apparently there have been some changes.
Apparently there have been some changes.
KiCAD 8 is a way inconvenient if to compare with KiCAD 6.
https://forum.kicad.info/t/introductory-videos-on-simulation-with-ngspice-in-kicad-8/48621
https://forum.kicad.info/t/simulation-examples-for-kicad-eeschema-ngspice/34443
https://forum.kicad.info/t/simulation-examples-for-kicad8-eeschema-ngspice/45546
These maybe of help.
I have not done simulation, but I have designed and tested boards with KiCad 8.xx. I think I started around 2015 with 4.XX or 5.XX. I do not have a problem with 8.XX although I will not say that I like all of the changes.
Sometimes I feel like the pop up thumbnails in footprint and symbol editors get in the way of whatever I am trying to do. Sometimes there is “too much help.” Sort of like helping the old lady to cross the road even if she does not want to go. Now it is more of a conundrum because I am an old man… 
Some time ago I thanked the dev’s for a feature which I really like. Could not… OH!! now I remember! Let’s say you have a capacitor connected to an IC pin. When KiCad names the net, it will now use the IC pin name instead of “C13 pin 1”. Older versions would use the capacitor pin number. For me, this is a serious improvement. Normally I do not pay any attention to pin numbers on resistors and capacitors, although it has some relevance for polarized capacitors.
I started my simulations couple of weeks ago. If I would be at home I would do it on breadboard with much less effort than I try to do it in KiCAD. Though two weeks ago I thought otherwise.
In my last contract job we used LTSpice to simulate the heck out of everything. I did feel that it would often be more efficient (or much faster) to go to breadboard sooner as a “sanity check”. But it is more difficult to change capacitor ESR or inductor characteristics on a breadboard.
If you have not a buggy part models of your sim it is, yes, easy way. But when they are buggy or missing on some reason by a manufacturer. Breadboard is a good solution even with its shortcomings.
Back to the circuit power-pc-board, which has been the source of lamenting about simulation.
I agree that breadboarding would have been much faster in achieving the goal of - killing voltage regulator U1, with its output rigidly short-circuited to ground.
After starting an op simulation, ngspice issues a warning:
Warning: singular matrix: check node probe_int_probe_int_net-_c7-pad2__c7_c7_2
Looking at pad 2 of C7, compared to pad 2 of C6, there is a difference: a missing ground connection.
What is the role of V2? To do this with breadboarding, you would need an advance digital signal generator with a few W output power capability and steep signals (2ns rise time at 5 V). In this circuit configutration it surely would help killing U2 and U3 as well.
I had an idea as timestep too small is coursed with incorrectly connected VPULSE.
I corrected the circuit diagram and “trouble with node “c4:power”” did not go away.
doAnalyses: TRAN: Timestep too small; time = 1,59412e-06, timestep = 1,25e-20: trouble with node “c4:power” run simulation(s) aborted
power-pc-board-corrected.7z (15.7 KB)
I removed R7, R8, D7, D6 and “trouble with node “c4:power”” does not bother any more. Timestep too small persistently exists though.
That circuit has a few problems. Why don’t you try to simulate it step by step i.e. first the voltage regulator, which probably doesn’t do what you intend to do. And then the mosfet driver, which you are driving outside of its spec with 10ns pulses, which means whoever build the model for it probably also didn’t intend it to be simulated like that.
datasheet says Input: 100 kHz, square wave, tRISE = tFALL <= 10 ns
Exactly, but your pulse is y1=0 y2=1 td=2n tr=2n tf=2n tw=5n per=10n and a 10ns pulse width is 100MHz, so you are off by a not insignificant factor 1000. There is no way this model will give you any useful result. But as I said, you should go step by step and first see if the voltage regulator works as intended.
Well, today I managed to catch the point of your saying!
This error pops out when there is a mistake in your circuit. The error provides you even with a node. How and where to look for that node I will rise in my next topic.