Thermal pad involving vias

The blue is solder mask which sits on top of the PCB copper but is only present where the solder paste is not to go.

The following illustrates the model with display of the (silvery-grey coloured) solder paste suppressed.
As seen, the blue solder mask consists of 5 elements sitting on the copper of the PCB.
It serves to restrict the ability of the solder to cross the mask and get into the via holes.

Does not “the grey area in the Kelly et al.” show where they are proposing paste to be?
So, yes I have the solder mask corresponding to Kelly’s grey area.
The only difference from Kelly is that my solder paste extends to the edges of the thermal pad.
As previously mentioned, I can suppress it by around 0.1 mm from all of the perimeter edges - that would make it look more like in the NXP datasheet and also as the example Kicad footprint.

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@Piotr wrote:

I have read that the paste tends to stay in the sharp corners of the openings in the paste stencil.
If the corners are rounded paste stays on the PCB when stencil is picked up.
A dirty stencil can lead to a shorts on the next PCB.

Yes, I can round the corners of the solder paste …
I can also use rounded rectangles for the 28 pads in Kicad.

I read on a web site that solder paste can typically range from 0.05mm – 0.15mm thickness.
My model uses 0.125mm which emphasises that the paste is much thicker than the solder mask (factor of 10x).

JLCPCB web site states:
Standard thickness of stencil like 0.1mm, 0.12mm, 0.15mm, 0.18mm, 0.2mm are for free.
The none-standard thickness will cost you: …

I don’t know what you mean by “If thermal pad is 0.1mm …”
Do you not mean “If solder mask is 0.1mm …”? Surely the thickness of the “thermal pad”, i.e., the copper is not relevant to coverage?
Since solder mask is much thinner than the paste then, in theory, an excess of paste may flow onto the mask and/ or into the vias (either that or the chip has to float up!). The other possibility is that the excess of paste would flow outside of the pad area.

Solder mask in the Fusion model is 0.0126 mm (JLCPCB state: Solder mask thickness 10-15um).
So the paste in the Fusion model is 10x thicker than the mask layer!

The bottom of the IC is slightly above the bottom of the 28 pads, refer data sheet.
A1 is 0.1mm nominal (ranging from 0.05 to 0.15mm).

So if a 0.2mm thick stencil is used with 50% of the thermal paste area being covered by solder paste, in theory either the IC would float up to be 0.2mm above the copper or the solder would flow over the solder mask (which it would be reluctant to do) or into the vias!

If a 0.12mm or 0.15 mm stencil was specified for JLCPCB whilst the solder paste covered 50% of the area then the IC should remain at around 0.1 mm above the copper whilst there would not be an excess of solder wanting to go anywhere?

I don’t understand what you mean by “pads can be ‘mask defined’”.
Is not the stencil aperture fully defined by the solder paste in Kicad F.paste?
Or is there a Kicad setting in which an offset can be specified?

It’s the same as “SMD windows”. Here SMD doesn’t stand for Surface Mount Device but Solder Mask Defined. The other option is Non-SMD which is a normal pad where the copper itself forms the land area. In a SMD pad the mask surrounds the land area and is partly on the copper, so the copper is larger than the land area. Interestingly, if you put for example a resistor footprint on a zone with solid connection or use very thick trace you accidentally form a pad which is a bit larger than a normal pad and which is Solder Mask Defined.

Where is ‘the same as “SMD windows”’ to be found in Kicad?

Is it Pad Properties … Pad type …?
In the Kicad footprint I mentioned, the solder paste pad is shown as being Pad type “SMD Aperture”.
“SMD” is another option in the Pad type drop down.

How does “SMD Aperture” differ from “SMD”?

Is the Kicad terminology “Surface Mount Device” or “Solder Mask Defined”?

It was only example value but important is longer text: “is 0.1mm over PCB”.
When you put IC on any flat surface it will be touching it with its pads. But its thermal pad is on some height over that surface and I was writing about that height.

No, in that place I was not considering mask in any way. Copper under thermal pad is at the same height as the copper under other pads but IC pads are touching copper but thermal pad is in some distance over it. At least I understand it that way. I just about 8 years ago had to use IC with thermal pad for the first time and read some appnotes and it is how I imagine it.

So exactly as I have assumed in: “If thermal pad is 0.1mm over PCB”.

No. You have to not understand something basic.
You have 100% thermal pad size.
You covered 50% of it with 0.2mm paste. So in average you covered thermal pad with 0.1mm of paste.
If distance between IC thermal pad and copper thermal pad is 0.1mm then everything matches and there is no too much paste to flow anywhere.

I added it only to not loose precision of my speech. To clarify that I am thinking about 50% of area of thermal pad (copper thermal pad) not covered by mask and not 50% of whole thermal pad (including parts covered by mask). Specially as you are trying to cover thermal pad partially by mask.
Copper pad can be smaller then opening in mask (not sure how it is named - copper defined pad), or opening in mask can be smaller then copper (mask defined pad).
Copper pad and opening in mask should not be the same. It is because of tolerances of placing mask at PCB. What would be the consequences if at one side mask will be partially on pad and on other side mask will start some distance from pad I don’t know. I just read that designing PCB you should clearly define pad by mask or by copper. I don’t know why sometimes in IC datasheet they write to use mask defined thermal pad (default for me is to have smaller pad then opening in mask).

Yes it is but it has nothing to mask.
When you get PCB from its manufacturer you can say this pad is ‘mask defined’ and this not (most are not). You need not to have stencil even manufactured to be able to say that so stencil has nothing to it.

KiCad doesn’t have any special property for that. The difference is only in the size of the mask opening compared to the copper pad. See How does solder mask layer work?. You can find more general information about NSMD vs. SMD by a simple internet search, for example “solder mask defined pads”.

Well, you mixed it up :slight_smile:

Excuse me, what? I don’t find anything which is mixed up.

As far as I know, every occurence of SMD in KiCad refers to Surface Mount. “SMD” isn’t used for Solder Mask Defined in KiCad. Having the same TLA in the industry to mean two different things which still are somehow related (both being used of pads) is of course very, very unfortunate.

“SMD Aperture” means a KiCad pad which doesn’t have copper but is in some other layer (and doesn’t have a through hole, therefore “surface mount”). Normal KiCad pads have copper and the possibility to choose some other layers. Normally both Mask and Paste are selected for a Surface Mount pad.

You should also get familiar with these Pad Properties:


And these board settings:

So exactly as I have assumed in: “If thermal pad is 0.1mm over PCB”.

We are in agreement with everything that you wrote up to here …

There was a misunderstanding about the terminology “thermal pad” - I thought that you were referring to that which was being laid out on the surface of the PCB (i.e., the footprint under discussion),
whereas I now understand that you were talking about the metal tab on the bottom of the IC.


So if a 0.2mm thick stencil is used with 50% of the thermal paste area being covered by solder paste, in theory either the IC would float up to be 0.2mm above the copper or the solder would flow over the solder mask (which it would be reluctant to do) or into the vias!

No. You have to not understand something basic.
You have 100% thermal pad size.
You covered 50% of it with 0.2mm paste. So in average you covered thermal pad with 0.1mm of paste.
If distance between IC thermal pad and copper thermal pad is 0.1mm then everything matches and there is no too much paste to flow anywhere.

Your interpretation assumes that the solder will flow equally wherever, even over areas of solder mask.
I am not sure that such an assumption is valid.
The solder will flow according to the principle of ‘least resistance to the flow’ - whatever that may involve?!

In my example, 50% has solder mask which the solder would presumably have some difficulty in spreading across and getting into the vias (that is a specific design objective).
So, more likely the excess of solder would either lift the IC (thereby impacting on soldering of the 28 pins) or spread out to the sides? (Or maybe some could jump the solder mask and get into the vias?)

If, in contrast, the solder paste is only 0.1mm thick, then regardless of the percentage area covered by the paste ‘everything matches’ - assuming that the solder doesn’t flow away from the defined areas of the solder pads - which is the intention according to the grand plan!

I need to ponder further on the remainder of your comments relating to “pads can be ‘mask defined’” and also those of @eelik
I admit to being confused by many aspects of the Kicad possibilities and how footprints are specified in Kicad …

I just used Google translator and assumed that the form I got is the English substitute for my a bit of a joke sentence.
I wanted to say: "And… you put here a mess in this conversation :slight_smile: " but in a very short form (in Polish: “I namieszałeś.”

This is a simplification, but it is close to the truth. The surface tension will melt it all over the thermal pad.

But I found what you don’t understand. Copper covered by mask is certainly not a pad area anymore.
If you have a bigger copper rectangle and on it a smaller rectangle opening in mask then you have ‘mask defined’ pad. The pad size is defined by mask = pad is the opening in mask and not the whole copper rectangle under it.
So if I write “you have 100% thermal pad size” that means only copper not covered by mask. And specifying that you have 50% opening in stencil it is 50% of those 100% copper not masked and not the whole copper if some of it is covered by mask.

If you covered 50% of copper with mask you have pad 50% smaller. So 50% in stencil will be 25% of what you count as a pad (what will be 50% of real pad).
If you want to name copper covered by mask a pad then all tracks at your PCB are pads. It leads to absurdity.

You should do it at once and not in some time in the future because it will be difficult to understand each other.

Well, this is a good example of why this whole discussion is difficult. There are component pads, there are copper pads, then there are KiCad pads which aren’t neither… It’s surprising how confusing the terminology may be if you go to details and try to talk about many things at once. Take a look at this: Land Patterns vs. Footprints: What’s the Difference?. So, what is a “footprint” of KiCad? It’s actually a land pattern plus something else, but not a footprint of a component.

What you call “pad” is a land pattern copper area where a component lead/pad is attached to, but when we talk about pads in KiCad we mean a technical drawing implemented in a certain way and defined with a certain user interface and having a layer/layers where each layer may have an area of different size.

I think I’ll stop now and leave Douglas to ponder these things. Otherwise we both go crazy.

I’m in my phone, so it’s hard to read and respond to everything, but one thing I saw needs to be addressed.

Under no circumstances should you have solder mask under the thermal pad of the IC.

The shape/size of the pad and location of vias are all a separate issue, but make the pad free from solder mask.

@3Dogs wrote:
Under no circumstances should you have solder mask under the thermal pad of the IC.

One of the starting points of this thread was consideration of the paper by Kelly et al. which proposes a “New Option 6: SMD Windows”.
This and the “five primary design options have been recommended by IPC-7093 and component supplier guides” are illustrated in their figure 6.
The caption to that figure defines green as being “solder mask”.
Of these, methods 3, 5 and 6 involve solder mask.
(Via tenting (option 2) also involves solder mask - in that case covering the via holes)

Looking at, for example, option 3 it involves solder mask covering the majority of the area.

I did a quick google for “Encroached vias” …

PCB Vias - Everything You Need To Know.
PCB Vias - Everything You Need To Know - Epec’s Blog
Encroached vias have solder mask over most of the pad but the mask stops short of the hole by a few thousandths of an inch.
This is a good compromise on medium-density PCBs between a full plug and doing nothing at all.

I have yet to read this article or become a fan of such vias … I am simply citing it to demonstrate that solder mask under the thermal pad may not be a “no go” as you are telling us.

What is the rationale or information source on which you base the claim that “under no circumstances should you have solder mask under the thermal pad of the IC”?

I shall continue to study literature and the details of how footprints are implemented in Kicad during today.
Up until now I have used Fusion 360 to model some possibilities - that has the benefit of assisting in understanding of basic principles without getting confused by Kicad implementation details.

I now need to understand aspects such as “pads can be ‘mask defined’”, the “Pad properties” and “Board settings” mentioned by @eelik, i.e., how to implement footprint details in Kicad.

A 40s search on the magic net coughs up the site below which explains this quite nicely.

Thanks for this link.

The difference can be understood as being whether there is a positive or negative overlap of the solder mask relative to the copper.

I understand the distinction but have little idea how to implement in Kicad!

Are there particular examples of implementation of each type in standard Kicad footprints that I can usefully study?

Apparently there’s already too much information in this thread, because I told in a previous post how to find more about (Non) Solder Mask Defined, and I gave a link to a FAQ post which tells how to create a SMD style pad in KiCad. Please read carefully.

I can attach and analyze a footprint later. I don’t know if KiCad libraries have Solder Mask Defined footprints.

Here’s some more information: Solder Mask Smaller than Pad

Here’s the current datasheet for TI CSD13383F4:, and here’s their technical document for the FemtoFET packages:

See how the recommendation is to use SMD style instead of NSMD. And interestingly the paste stencil openings are offset from the land pattern. There would be much to analyze in this, and even more if you want to use this in manual assembly (yes, it’s possible! But I had to modify the footprint for that) or use cheap and not so advanced manufacturer.

Here’s the final footprint:
TI_MOSFET_F4YJC_0402_FEMTO.kicad_mod (2.7 KB)

Yes, I am suffering from information and ideas overload :frowning:

Regarding the thermal pad, I am not sure if the subject of Copper Defined Pads vs. Soldermask Defined Pads has much relevance.

The thermal pad starts as a simple rectangle of copper on the PCB.
Overlaid on top of that are the vias, either with or without solder mask surrounds.

Without solder mask surrounds is what Kelly et al. describe as “Option 1: Open copper”.
In this case, solder paste blobs are being laid onto the open copper. Nothing defines the paste blob size other than the geometry of the solder blob (the stencil cut out).
So neither NSMD or SMD applies - since there is no solder paste, whilst the copper layer is continuous!

With solder mask surrounds of the vias is what Kelly et al. describe as “Option 6: SMD Windows”.
So, yes, they could be considered as being SMD solder paste blobs - but since the solder paste is sitting on top of the overall thermal pad, the subject of overlaps only arises at the edge of the thermal pad.
Then, whether of not there is a positive or negative overlap of the solder mask relative to the copper arises.

My Fusion 360 model was only considering what was happening within the thermal pad.
I didn’t consider solder mask at the edges - so the subject of NSMD or SMD seems to not apply.

If (as I was proposing to do), I offset the solder paste from the edges, that is achieved by having a positive overlap of the solder mask at the edges to cover a little of the edge.
Then we have an SMD-type pad edge.

This provides clearer drawings to illustrate the difference between NSMD and SMD pads, whereas the link provided by @paulvdh covers the pros and cons of each.
Whether a pad is of NSMD or SMD type clearly applies to the 28 pins of the IC - but my understanding is that such terminologies are of little or no relevance to the thermal pad, other than how the solder mask may or may not overlap the copper pad at its perimeter edges.

These TI documents (which I have yet to study in detail) reinforce my impression that the terminology of NSMD or SMD is only of relevance at the edges of copper pads.

It seems fruitless to consider what type of definition terminology to use for a solder paste blob sitting within a copper surface, the edges of the blob being defined by solder mask/ the stencil.
For such, only SMD can apply.

Only at the perimeter of the copper pads are the alternatives of NSMD or SMD available, depending on whether there is a positive or negative overlap of the paste relative to the edge of the copper.

In what regard is this whole thing relevant to what you are doing?
KiCad’s default footprints are fine for most general work. Have you actually encountered some problem that you need to fix? Just because some Kelly guy somewhere on the 'net has a proposal for some complicated thermal pad design does not mean you have to implement or even read it.

Same for those (Non-) Solder mask defined pads. It’s good to know those solder mask pads exist, but I’ve never used them myself, as far as I know they are used in some “special cases” but I don’t really know (nor care) what those situations are. So why spend (much) time and effort on the topic at all?