Schmitt trigger relaxation oscillator sim


I am trying to use kiCAD’s ngspice to simulate a simple Schmidtt trigger (40106) relaxation oscillator for a synthesizer project.

This is my schematic:

I am using the 40106 pspice model from TI as the parts I have on hand are from TI (and I can’t find an alternative spice model for the 40106).

I have mapped the pins to the spice model and set pspice compatibility mode.

The problem/s:

  1. When I try to run a transient (10us step over 0…1s) I get this error:
doAnalyses: TRAN:  Timestep too small; initial timepoint: trouble with xu1.xu1:d1-instance d.xu1.xu1.da2`
run simulation(s) aborted

Casting about I found this stack overflow post that mention that models often lack a parameter for the gate’s propagation delay (td).

  1. Trying to add .PARAM td = 10e-9 to the model results in:
    Error: No model named " in library
    This specifically occurs if I re-add the .lib model to the schematic symbol after adding the td parameter.

I’m a bit lost at this stage. I’ve mainly used LTspice and multisim in the past but not with much formal instruction in how they work.

I am I misunderstanding the stack overflow post? Should td be a simulation level .PARAM not added to the model directly? Is the problem something else entirely that I am failing to notice?

I cannot answer your question…I have been using LTSpice but I am no expert with it. However a couple of years ago I made a similar oscillator on a test board using a (I think it was a SN74LVC1G14) schmitt inverter. It ran OK except that it was drawing 15 or 20 mA of current. At 5V that approaches 100 mW which is sort of high. I think that the oscillator keeps the input in a mid voltage crossover region, and the input transistors draw relatively high current in that condition.

My take on that is that it is OK for experimentation, but it might not be a good design to use in a product.

Also the frequency of this oscillator will not be so accurate because the hysteresis is not precise.

Based on your 100 nF timing capacitor, I think you might be better off to use a voltage comparator (such as something from this list) instead:

This link actually points to a comparator oscillator circuit. It is time proven and very accurate:

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I don’t see a spice power supply (e.g. VDC from Simulation_SPICE) in your circuit schematic.
.tran 1u 1m immediately gives me this (KiCad 7.0.6):

EDIT: Unfortunately the generated output is wrong because in and out pins of the 40106 are interchanged.


@holger Well that is embarrassing. You are most certainly correct and oddly my install of kiCAD () seems to only have the 0V reference symbol in the simulation_SPICE symbol library.

I’ve tried copying the Simulation_SPICE.kicad_symbol (223.1kB) and Simulation_SPICE.sp (350 bytes) down from the kiCAD gitlab repo, removing the old one, and then even re-adding the library to the library table as a new library named SPICE. Yet, all that I see in the power symbol picker is 0V (in both the new and old entry).


Both of the those libraries live in usr/share/kicad/symbols/ and If I open up Simulation_SPICE.kicad_symbol in a text editor I can see other symbols defined in there other than 0V, eg:

  (symbol "ESOURCE" (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes)
    (property "Reference" "E" (at 0 0 0)
      (effects (font (size 1.27 1.27)))
    (property "Value" "ESOURCE" (at 12.7 1.27 0)
      (effects (font (size 1.27 1.27)))
    (property "Footprint" "" (at 0 0 0)
      (effects (font (size 1.27 1.27)) hide)
    (property "Datasheet" "" (at 0 16.51 0)
      (effects (font (size 1.27 1.27)) hide)
    (property "ki_keywords" "simulation" (at 0 0 0)
      (effects (font (size 1.27 1.27)) hide)
    (property "ki_description" "Voltage-dependent Voltage source symbol for simulation only" (at 0 0 0)
      (effects (font (size 1.27 1.27)) hide)

I’m not sure what I’m missing here.

@BobZ I appreciate the heads-up. This is more of a personal project to get my feet wet with some synthesizer circuits. Imprecise frequency for noise box isn’t too big a concern.

That does sounds like an awful lot of current. This was just a single oscillator or all six in a package going? I’ve read a few app notes (such as this one from Fairchild) that specifically describe this style of RC relaxation oscillator as low power". This being said, those app notes weren’t terribly specific on what qualifies as “low power”.

I currently have three oscillators wired up and cascaded together on a breadboard. I will have to take a look at how much current is being drawn.


That device I mentioned is a single inverter.

This is only the first reference I could find and probably not the best. From a Nexperia datasheet for 74LVC1G14:

Basically this shows relatively high supply current when the input voltage is in the hysteresis/crossover region. I think that 5V would be worse than 3V.

And BTW I have been testing circuits for many years. IN MOST CASES performance is improved when input voltage is applied. Unfortunately that usually increases power consumption. :crazy_face:

The Power Symbol picker is not the right choice.

Open the Symbol picker ("Add a symbol), search for VDC, scroll down to Simulation_Spice, choose that symbol.

To be honest, not very intuitive. This would be worth opening an issue as a feature request at Issues · KiCad / KiCad Source Code / kicad · GitLab.

Not intuitive perhaps but I probably should have thought to look in the regular symbol picker too.

This is now what my setup looks (I am on kiCAD 7.0.6 - think I had forgotten to state that):

Everything has spice models. I have set the simulation DC Voltage to 5V, check compatibility: pspice, rerun .tran 1u 1m and I am still getting:

doAnalyses: TRAN: Timestep too small; initial timepoint: trouble with xu1.xu1:d1-instance d.xu1.xu1.da2 run simulation(s) aborted

Here is the console output when I try to run the sim:
spice_sim_console.txt (24.2 KB)

@BobZ Neat! I wouldn’t have thought to go looking for a transconductance graph in the datasheet.

My breadboard (three games oscillating and three with inputs to ground) at the moment draws between 0.84-6.9mA depending on how much I trim the feedback pots. That is of course unloaded on both the input and output :stuck_out_tongue:

I will have to have a think about optimizing some RC values so that the power draw is a little more reasonable.

OK I was unfamiliar with “40106”; now I see that it is from the original CD4000 CMOS family. That is much slower than the IC I was discussing and it is reasonable that the supply current per gate input would be reduced. But if the current is varying significantly with potentiometer setting then that potentiometer must be conducting significant current as compared to the IC supply current draw. There should be no problem to increase the resistance by 10x and decrease C1 by 10x.

When you look at the console output, “last voltage” is everywhere 0, so there is no voltage on your circuit.

First step: put a GND symbol to the negative port of V1. VSS of U1 has to be grounded. Spice is delicate about missing ground connections.

If still not o.k., post the spice netlist here:
Eeschema–>File–>Export–>Netlist…–>Spice–>Export Netlist

CMOS Schmitt Icc is also heavily dependent on Vcc
Here is an example from 74HCS14

and this is HEF40106 at 5V, it will be lower again at 3v

You can also lower Icc more, if Icc is critical, by change of the oscillator design.
The simplest RC model operates between those two peaks, but you can use 2 gates and make a 2R-1C oscillator (see HEF4060 et al) and that can have lower Icc as the Vin sweeps a wider range.

Oh my goodness :man_facepalming: I had a 0V spice symbol on there but I see now that I must have absent mindedly deleted it in my rearranging of the schematic. I appreciate the patience and assistance.

I have made the adjustment and now look like this:

I still get the same error. However I have noticed if I try to look at the simulation mode via the symbol properties menul for the 0V simulation_SPICE model I get this error:

Error reading simulation model from symbol `#GND01`:
Failed to read simulation model from fields.

Not sure if that is part of the problem
Here is the SPICE netlist:

.title KiCad schematic
.include "/home/parablennius/Documents/synth/schm029a/CD40106B.lib"
R3 /Sync Net-_R3-Pad2_ 10k
C1 /Sync 0 0.1u
XU1 /Sync Net-_R3-Pad2_ NC-U1-0 NC-U1-1 CD40106B
V1 Net-_U1G-VDD_ 0 5V

I shall be gone camping till next Monday.

@BobZ you are correct. I don’t have a second resistor to set a minimum current with the pot trimmed all the way down (would certainly help).

@PCB_Wiz do you by chance mean this design when you say 2R-1C oscillator:

From the ST HEF4060?

The waveforms look like this, more time is spent away from the current peak region at VIN node.

Also, the frequency does not vary with the supply voltage, unlike the single Schmitt version.
If you use a gate, as @PCB_Wiz illustrates, you are also able to switch the oscillator on and off with (in the example) pins 2 or 5.

Edit: and the output is the full supply voltage swing, not just the upper and lower hysteresis as Bob mentioned and Holger demonstrated.

It is instructive to read the spice netlist. This netlist is generated by Eeschema from the circuit diagram and is sent to ngspice for simulation. It is all about devices, connections and values.

Take voltage source V1:

V1 Net-_U1G-VDD_ 0 5V

V1 is the device reference (V for voltage source). Two net connections (nodes) are following, Net-_U1G-VDD_ and 0, then the value 5 V. Unfortunately this source is not connected to anything. There is no second Net-_U1G-VDD_ anywhere in the netlist.

It should be connected to devices U1, whose instance in the spice netlist is

XU1 /Sync Net-_R3-Pad2_ NC-U1-0 NC-U1-1 CD40106B

which is a call to the subcircuit in the model file CD40106B.lib, which is included (thus loaded into ngspice by .include command). The model offers the subcircuit


without telling me what might be input or output (Y or A), but with VCC as power and AGND as ground. I have chosen Y as in, A as out. The XU1 instance line does have two nodes

NC-U1-0 NC-U1-1

again not appearing again anywhre in the netlist and thus again connected to nothing.

So something went wrong with your setting up the device U1, e.g. with the pin assigment.

My netlist is

.title KiCad schematic
.include "D:/Spice_general/KiCad-700/rel_osc/CD40106B.lib"
.tran 1u 1m
R1 /out /cc 10k
XU1 /cc /out /vdd GND CD40106B
V1 /vdd GND DC 5 
C1 /cc GND 100n

and my project (KiCad 7.0.6) is
rel_osc.7z (9.4 KB)
where you also may see the correct pin assignment.

EDIT: still in and out of the 40106 are interchanged.


My above assumption was wrong, so correctly: A is in, Y is out.
The resulting graph looks much better (signal /cc is in)

The time constant of 10k * 100n = 10-3 is met approximately, the output is a pulse with amplitude 0 to 5 V. The updated project is here
rel_osc_updated.7z (9.5 KB)

EDIT: just renamed the above project.

And a little playing around with the many inverters: 3 Oszillators at different frequencies, each with an output buffer:

and the project
rel_osc_mult.7z (11.1 KB)

And here are three different frequencies in a single simulation run, using a behavioral capacitor

rel_osc_sequ.7z (9.6 KB)

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Alright, okay, I’ve got the simulator running (VSS and VDD were indeed assigned to the wrong pin) although the sim is not yet giving the expected output.

I see this on the input (cc) and output net (out).

If I run either your project’s simulation file or my own simulation I get the same result.

My netlist now looks like this:

.title KiCad schematic
.include "/home/parablennius/Documents/synth/schm029a/CD40106B.lib"
.save all
.probe alli
.tran 1u 1m
R3 /cc /out 10k
XU1 /cc /out /vdd 0 CD40106B
V1 /vdd 0 DC 5 
C1 /cc 0 0.1u

That is about right. Much the same as Holger’s red signal.
The blue trace is only available after that signal has passed through a buffer, see Holger’s schematic.

You are still better off with your posted “Fig 6” or @PCB_Wiz s top schematic - frequency is less voltage dependent.

I have edited my posts above, and I have renamed my updated project to make the steps during development more obvious.

This is not correct. Did you run the simulation with the updated project before posting?

XU1 /cc /out /vdd 0 CD40106B

from the above post is still wrong, if you compare the node sequences of of this x line (… /cc /out …) with the .subckt line of the model (… Y A …), where correctly A is the input and Y the output.

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No, used real life - breadboard & CRO, but stupidly, after checking, found I was measuring the top of the cap. ie. the input of the schmitt.

Appologies for the noise.

B.t.w. running the simulation with my projects is as simple as this:
Download the *.7z and expand it into a place of your choice.
Start Eeschema (7.0.6)
Search for the *.kicad_sch in the previously expanded directory
Open the file in Eeschema, thus loading the project.
File–>Open Workbook
The simulation starts immediately and plots the result. (In my Windows 10 installation afterwards I need to right click into the plot window and then call ‘Fit on Screen’ to scale the plot correctly).

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