Eyyyyy, finally got it (on both mine and your simulation - I had grabbed the original file not the updated)! Thank you so much!
You were once again correct the input and outputs were swapped. I could have sworn I tweaked that last night but I guess I didn’t (looking at the circuit first thing with coffee in hand definitely helps).
Lots of little things to keep track of. May I ask how you spotted the error?
Is part of the spice work flow just always checking the model file against the netlist to ensure that they match in order? Or do they have an explicit order?
From the model file:
.SUBCKT CD40106B Y A VCC AGND
From the netlist:
XU1 /out /cc /vdd 0 CD40106B
Should the above always be out in pwr gnd or is it just that the two should match in terms of order? Is there some way to run an ERC or have the equivalent of compiler warnings for spice?
Or am I failing to intuit that hooking up a RC network to the output of the Schmitt trigger would yield an identical triangle wave on both in and out?
As mentioned previously, while I have used spice simulators at Uni (multisim and LTSpice) there has been zero formal instruction in spice itself. Does anyone have any recommended reading on the topic? Other than the ngspice manual I suppose?
@jmk The plan is definitely to pivot to the 2R-1C style oscillator. I just wanted to be sure I could get the simplest implementation working with the simulator first 
. Bad for momentum but this is as much a learning exercise for me as trying to build myself an oscillator.
