Hi experts,
In my project, the pcbnew is showing an unconnected Ground pin and a Ground zone. The DRC control for unconnected pins of course confirms it.
The pin in question is the pad 1 of the capacitor C4 and the unconnected zone is apparently under U4.
I have made various attempts to overcome the problem by placing vias and/or even directly connecting the capacitor pad1 to Ground the problem remains. I must be missing something. If possible I would like to avoid a complete new P & R.
Could someone please give me a hint on how to solve the problem short of having to do a complete new P&R, please? For your reference have attached four files as follows:
First: The whole PCB layout is pretty bad, As many beginners, it looks like you have not learned yet what GND planes are, and how they work. You really should be doing some reading about this.
Your problem is pretty simple to solve.
It’s so trivial that I’m afraid I’m overlooking something.
KiCad recognises the pin as unconnected, because it is, well, unconnected
Even though you’ve put in “zones” on both side of the PCB.
On the bottom ob the PCB, the area I encircled in Yellow only connects to a single pin.
The end result is that pin 5 of U4 is not connected to anything but these floating zones. Just placing a via at the blue cross will connect the small encircled area’s to the other pins of the GND net and the error message will go away.
But it will not solve the bigger problem, of not having a decent GND plane.
For a good GND plane, One of the sides should be (nearly) completely dedicated to attaching the GND pins of all IC’s together. As is, your PCB will probably work (I have not looked at the schematic) but it’s far from “good practices”
Hi paulvdh,
thanks for your honest and frank response - and for showing the solution.
You are right, I am a beginner and have a lot to learn. For me, besides having the solution, it is equally important to learn as to how you looked on both sides to detect that only one pin was connected and that the zones are floating.
I tried to place a via in a zone area where they were not overlapping and probably therefore the connection failed.
I read useful links given in answers to questions raised in the KiCad forum and watching YouTube videos on KiCad (e.g. John’s Basement) etc. I have learned a lot from them. But, what appears to be “trivial” for you and how you approach a solution, is for me perhaps lack of experience.
This of course is no excuse for me and I would like to thank you sincerely for your prompt help.
If you have a link to some good reading suggestions on layout issues, kindly let me know.
As is, your PCB will probably work (I have not looked at the schematic)
From an electrical and logical point of view, the circuit should be ok. I have tested it on a breadboard.
However, even I am not quite happy with how the PCB layout looks like currently. PCB size is certainly one issue - for me at least. However, In the light of your comments, I may decide to redo the layout from scratch anyway.
Thanks and best regards.
I was a beginner once too.
It was before the Internet happened…
There is a lot to learn about PCB design, and on top of that there are all these new EMC rules for the last 20 years or so, and electronics getting much faster then the TTL stuff used to be.
In this recent thread Piotr posted a multi part PDF about … this topic.
I have not read it, but there are multiple books about related topics, and a few simple search words will cough up many more results.
A few simple hints:
Try to make as big as continuous copper on one side, and use it for a “Ground Plane”.
Interruptions in this plane should be as small as doable.
Whenever there are area’s in your “Ground plane” that are getting bigger than about 10mm, try to make make a bridge on the other side of the PCB to “stitch it together”.
Ideally each copper track that has high frequency content, has a uninterupted groundplane directly beneath it. For your relatively low speed TTL IC’s it is however much less critical than for the newer high speed stuff (With speed, it’s the rise time, not the base frequency of the signal).
These are just a few thumb rules. For more in-depth information read books such as what Piotr posted.
Not probably, but for sure
I didn’t opened your design, I have only looked at pictures paulvdh posted.
I think:
You have to big clearance (probably the default one). For current PCB factories 0.2mm (or 0.25mm) is enough.
Your via seems for me too small copper but may be it is because of comparing it with tracks which may be are different width than I am used to and it is a source of incorrectly seeing via. For me typical via is 1mm copper diameter and 0.5mm hole (or 0.9/0.4) just to have some margin from PCB factories specifications. But I practically don’t use vias at signal lines (only at GND) because my designs are really one side (with GND at the other).
If you have smaller clearance the GND zone would leak between pads and you will be also able to route tracks between pads. For 2.54 raster you can change pads to have them narrower but longer. It still will be easy to solder. That way you can get 1mm distance between pads copper. With 0.2mm clearance and 0.2mm track width you are then able to route 2 tracks between such pads (I assume it a big help in design) and it is still easy to manufacture for all PCB factories. When I have done such experiments with KiCad (4.0.7 those time) I found that KiCad had a problem to fit two 0.2mm tracks when the gap was 1mm and clearance set to 0.2mm. The problem was solved by setting clearance to 0.199.
Hi Piotr,
Thanks for your tips recommending using reduced clearance, track width, and Via and its hole diameter.
Yes, I am using default KiCad values for all these parameters and I checked the KiCad ver 5.1.7 ( which I have used for my design), the default values here for clearance is already 0.2mm, but the Track width, Via: and Via drill (hole) parameters are different.
As I mentioned in my response to pauldh’s comment, I have now decided to redo the layout of my project for achieving a more coherent GND plane. Your tips are just in time. I will change the remaining three default values, i.e. track width, Via, and Via hole parameters also to the values recommended by you.
Thanks a lot for your tips.
Best regards
If you don’t want to add a new dedication connection (ie a via to tie to shapes together), there is one via that can be moved to provide the needed connection. Although changing the filled copper clearance rules would probably be better
For signal lines I typically use 0.25mm track width. But if in some places of PCB 0.2mm track would help I just change width to 0.2 locally. That is why I considered 0.2 to fit 2 tracks between pads.
But to do it you probably, as I have written also have to change pads (make your own footprint). If you don’t then 0.2 will have no advantage over 0.25 in your PCB I think.
I would also prefer 0.25mm clearance, but as you can’t set it locally I use 0.2.
