No, because they’re chopped to hell by all the components and the traces you still insist on routing there. There is no reason you can’t have one or even two completely solid (minus vias, keep them spaced out!) ground planes.
It’s also a bad idea for debugging/rework to route lots of traces internally.
Do you understand the purpose of a ground plane? It’s not just to have a bunch of grounded copper. It’s to ensure that every signal/power trace has a completely uninterrupted return path directly above/below it.
If you read articles I have linked some time ago:
you will understand what rules and why ground planes are expected to fulfill.
Wouldn’t hurt to be just a tiny bit less condescending.
I’ll read thru those, thank you.
It was an honest question based on your responses. I’m being blunt because you don’t seem to get it otherwise. Like the other guy said, why are you asking for reviews if you know best.
I do not know best, but also, your earlier comment makes no sense. Best practice according to most on here is 2 layer board and now you are saying two completely solid ground planes? How is that even possible?
A few contend that I need my traces on the top or bottom so that in the event there is a mistake I can fix it on the board. I said that with good testing, that shouldn’t be necessary. I’m not trying to say I know everything at all, just that I have all the time in the world to get the connections correct before committing this to copper. Which there is absolutely no reason at all that that is not a possibility.
I have doubts as to whether we have read the same text. For me it was obvious that halachal is speaking about your 4-layer board.
I have written something about my 2-layer strategy only because I have never designed 4 layer.
See figure 3 in:
http://www.emcesd.com/tt2002/tt120102.htm
You get 100mV between two points, both at GND only because singal is crossing the gap i GND,
I am reading thru the PDF’s right now Piotr. Thanks for that.
But you can’t test before you have the physical board. And if the prototype has hidden tracks…
Testing with something else than the final product isn’t usually enough. You can’t trust a breadboard or something like that.
This is a terrible reason to make that kind of design decision. Apart from that, a well routed board looks better than a one without traces. 
Later in the same thread I have linked other articles.
Point taken. I will say though, that with such a simple board (as others on here have repeatedly mentioned), testing should be trivial. 
I guess this is a preference.
Proper 2 layer design requires lots of experience and much more work (especially in regards to component placement, connections etc.). I frequently rearrange MCU pins only to get better layout so it’s time consuming, iterative process. The only advantage is cheaper PCB.
If you’re not going to mass produce your boards and if we’re talking single boards here 4layer vs 2layer cost difference will not be that important.
So stay with 4 layer but try to implement good advices given by experienced hardware designers who comment here.
By the way, I was having PM discussion and must change what I explained regardin the ceramic cap at buck input. Typically it’s crucial for good EMI, but according to the datasheet of your part the manufacutrer recommends good quality low esr electrolytic as extremely low ESR ceramic may lead to ringing (probably huge parasitic inductances).
I think that is called gate swapping! (I pull legs often but I am serious here…)
Indy: When I laid out a 4-layer board recently, I started out with a 2-layer board.
Once I had the parts where they needed to go and the signals laid out, THEN I added the internal layers, sending the ground / VCC to those layers as needed. It helped minimize the number of traces that would otherwise cut through the internal layers.
This is about as good as I can get it… just no avoiding jumping across some of the traces on the back.
So you managed to make it 2 layer with all components on one side? Great! The rest is much smaller details.
There’s one big thing which is repeated all over, but the solution is rather optimization than fundamental change. You have already added vias here and there to connect the ground zones in two sides. But you can add more of them and especially in strategical places. Look at this one:
You have an antenna there while you could use it for making a continuous plane. If you keep the traces as they are you can keep also the lower GND protrusion but add via or vias in the left and right (the start and end of the arrow). Then it creates a connection over the vertical trace which goes in the bottom side.
You could also move the traces to south and make a similar connection in north side of them (the upper arrow).
You should repeat this technique everywhere. The rule of thumb is that the vias are best in corners, even when they don’t add a new connection. I have marked some corners here:
Vias can’t be placed in all of these places. If you can place only one via which creates a new small filling (look at the area marked with yellow rectangle), it doesn’t add benefit. Rather delete the via and leave it unfilled.
You have used a long route here:
Why not try a shorter one? Jump over it using vias and the top side GND zone.
Maybe those two 45deg traces could be routed differently:
These are of course just examples.
Change the thermal connection of the mounting holes to solid unless you actually need to solder them.
An often used ans simple rule of thumb is to keep a continuous GND plane. A more correct reason is that at “higher frequencies” (even as low as 1MHz) the return paths of each signal take the path of least impedance, and for such signals the path of least impedance is not the DC resistance or straight lines, but it is dominated by the loop area between the signal and it’s return path.
If the GND plane is continuous, then (above around 100kHZ) the return paths of the signal currents will be directly below the signal because that has the lowest loop area and therefore lowest inductance.
In the screenshot below I drew the connections between the IC (U13?) to the connector on the left in bright red (on the other side), and the return path through the GND plane in bright green.
If you remove the track (purple cross) and lay it on the other side around the connector (purple line) then it removes an obstacle for the return current.
Another obstacle for the return current is the track marked in yellow. Maybe a part of this track can be moved to the other side, or else use via’s to give the return currents a shorter path.
There is “Field solver” software that can make calculations of how these return currents flow through the GND plane for different frequencies, and youtube has a bunch of vid’s of simulations with this sort of software, and some of these vids are made in the form of a tutorial and are worth watching if you want to know more about EMC and PCB design optimization.
There are a few more of such optimizations that can be made. For most of this PCB it probably is not very important, but when signals switch more often and frequencies (flanks) get higher (steeper) it becomes increasingly more important.
Now that you’ve discovered this actually CAN be routed in less than 4 layers, you can just add back in In1.Cu and In2.Cu as GND planes (perhaps with the addition of a few judicious stitching vias), and all the problems pointed out by the last few posters are immediately solved.
Of course a 2-layer board will be more economical but not by that much, so the proper choice depends on your production quantity and how you value your time.
Going from the latest interation back to 4 layer is certainly possible but would be silly. The design is quite near a decent 2 layer board at the moment, and understanding what the limitations are and fixing them will teach you more then just trowing in some extra layers.
For higher volume the price difference can be relatively small, but for small quantiies the price difference can be quite substantial (Especially compared to the EUR3 PCB’s from China.)
