Ah, the optimism of a first time designer 
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I don’t think even the best layout engineers can say they have never had to mod a board for one reason or another.
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I do have a couple of things in my favor, one is time. I am not under any kind of deadline to get this produced. Plus I have you guys to kick me in the ass and tell me when I’m wrong.
Well …interested… I wasn’t also … but I remember looking for a position where I could drill a 3mm hole that definitely breaks a track inside but doesn’t do any harm to the rest of the board… It’s faster and cheaper than making a new one 
I’d wager a lot of money that this is not true. Remember vias are free, and for most signals weaving back and forth several times has no negative impact. A general strategy that works well is to route signals vertically on top and horizontally on bottom.
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Another tip is where the device pin assignments are not set in stone (i.e., using a generic driver like a ULN2003A or a 74xx logic gate chip) is to consider swapping connections and gate assignments on the schematic and pushing that back to the board. I recently laid out a couple boards myself, and I solved a few routing pickles in the rat’s nest / part layout phase by swapping around pin / gate assignments on the glue logic ICs I was using.
Here are the changes I made. I moved all parts to the top, and changed front and back layers to be ground planes. I did leave a good bit of the traces in the middle.
I also fixed a couple of the JST connector pin assignments so they were all generally the same and labeled them. 2 of the 2 pin JST’s don’t require labels as they aren’t polarized. I changed the type of connector I am using on the ADC, but didn’t bother adding power and ground pins as there are power and ground pins on a connector just to the north of the ADC
I also moved all of the vias from the pads.
I changed out the DAK package on the schottky diodes in my buck converters. And swapped the electrolytic for ceramics.
I did not yet fix the ugliness on the schematic, but plan to. was more interested in getting the pcb fixed first.
GTReef.zip (790.3 KB)
You should use hierarchical sheet for these.
I’m still seeing a lot of traces on inner layers that really do not need to be on inner layers at all.
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One important part of PCB design is component placement, and the component placement of this PCB can be improved a lot.
Just have a look at U13 (PCA9685PW).
On the yellow layer a lot of tracks go from the center of the PCB to that ic, and on the purple layer they go from the connector on the left all the way to the IC on the right.
If you optimize component placement for better routing a simple board as this can be done on two layers.
Another issue are your rows of via’s. Because the via’s are so close together they make quite big holes through the planes in all layers.
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Agreed
I have just had a spare 20 mins at work free so have loaded your design and started re-tracking it using just top and bottom layers with a ground plane on one of the middle layers and although not pretty, in 20mins I have routed 80% of the board. I reckon with better component placement and switching of some of the pi io I could have completed it in 30 mins. Run out of time now though.
I don’t understand why you ask people to review the board and then not implement the improvements being suggested.
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I plan to when I revise the schematic
I’m sorry, I was not aware that just because I asked for a review I was required to implement all improvements suggested. I have implemented most of the improvements that have been suggested and will continue to do so…
I understand that component placement is important, I guess I don’t see where I’m able to move U13 to be close to everything that it needs to be close to. It connects to the 40 pin, the mosfets for the 5 2pin jst connectors and the 14 pin on the left. going to be impossible to keep all of those components next to U13 and still function the way I intend.
Does this look like a better way to do the vias??
In my designs component placement takes more then 80% of all time spend on PCB. That is probably because I design 2-layer PCBs with whole bottom layer used for GND. So I do all my connections (except GND) at top. In most cases before I start routing traces I know which way each track will go.
My ‘trick’ to avoid crossings of many tracks with VCC lines is to go with VCC under microcontroller and then spread it radiantly through its corners and all VCC pins.
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This is pretty much the price you pay for cheaper 2 layer PCB’s.
About the via’s, something like that is just fine. But most of the tips given here are mostly “rules of thumb” without the underlying theory (and there is a lot of that). Most is for reducing electromagnetic radiance. For this PCB it does not matter much, but when frequencies get higher (better: flanks of signals get steeper) it becomes more important.
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You obviously can do whatever you want, but it’s annoying when you ignore good advice and make silly claims. Fact is, your grounding is still shit and will continue to be until you dedicate a plane to it. There is no reason you need all 4 or even 3 planes to route the traces on this board.
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Please try to keep it friendly!
It’s okay to not like things…
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Know that.
When I will select the microcontroller in case not allowing to go under it with VCC I will use 4 layers.
so top and bottom ground planes are not good enough? I believe you may have missed the fact that last night I posted an updated version that changed a few issues like the ground planes.