PCB routing suggestions (Beginner)

[Spaceboy]

Hey guys, yesterday I asked a question about I2C and @paulvdh recommended me an awesome video by Rick Hartley on grounding. So after that redesigned my board trying as much as I could to do a solid ground layer. Are there any mistakes?
I placed all components on the bottom so as to reduce assembly costs. I run out of space if I try to place them on top.
The top side has three planes: two power planes and a ground plane. the power planes are for heat dissipation. If you suggest, I can remove the power plane on the right and replace it with a ground plane as I don’t expect heat to be much of an issue there.

The I2C routing:

A3 is the single wire data line of a DHT22. The trace above A3’s is an analog output.
(Oh wait just realised the DHT is a digital output and I should add some space between that trace and the analog trace)

Thanks!

[Piotr]

@Spaceboy

So after that redesigned my board trying as much as I could to do a solid ground layer.

The key is to understand which way return current of each signal is going back to the source. To have lot of GND planes may be not enough. If signal track jumps from being over one zone to be over second zone the return current has a problem and when it travels long way depending on circuit it can emit noise or be sensitive to interference.

If you want to learn PCB design my suggestion was to read:

Decoupling capacitor via placement

I didn’t read that book but I suppose you can replace it with: I think it is enough for most pcb designers.

and:

Decoupling capacitor via placement

About 2004 I found an interesting serie of EMC articles by Keith Armstrong (for many years I didn’t know if Keith is a woman or men name). Later they became no accessible, but when I tried to find them few years ago I found them once more: http://www.compliance-club.com/pdf/DesignTechniquesPart1.pdf http://www.compliance-club.com/pdf/DesignTechniquesPart2.pdf http://www.compliance-club.com/pdf/DesignTechniquesPart3.pdf http://www.compliance-club.com/pdf/DesignTechniquesPart4.pdf http://www…

and it (my suggestion) didn’t changed since that time.

My solution for 2 layers is to always have continuous GND plane at one layer. An example of such PCB I shown here:

Approaching PCB track routing for a newbie

Positioning for me is the main work in designing PCB. If each element is where it is needed than routing is simple. Till now all my PCBs are 2 layers and all of them have GND plane taking 100% of bottom layer. So except GND I design my PCBs as 1 layer. I use microcontrollers in QFP packages without thermal pad at bottom. This allows me to go with VCC under the microcontroller and go out through all corners and all VCC pins. That way GND and VCC don’t disturb my signal connections. At all digi…

[Spaceboy]

Yeah but the ones to the top are just switching signals to turn a moseft on and off. I’ve tried to route the communication traces over a part of a ground plane as much as possible.

[Spaceboy]

Can you suggest some ways to improve my board? Do I have to increase its size and put all components on top?

[paulvdh]

This already looks a lot better. For an arduino nano (which is a relatively old fashioned / old technology microcontroller) it does not matter very much and this looks “acceptable”.

However, if you want to use this as an exercise in optimizing the PCB there is still room left for improvement. For example, the green track below can easily be routed on the red layer, so there is a more continuous GND below that group of tracks:

When there is no possibility to do such things, you should still optimize the GND plane by moving the via’s closer to the track to reduce the opening in the GND pane and the size of the detour the current through the GND plane must make.

I see that you’ve placed some via’s in strategic positions. In the corner of planes to stitch them, and near via’s in signal lines. This is good, but you have not done this everywhere and you can do some more of these. Via’s are essentially free (unless you really have an excessive amount of them).

These two parts of your GND plane are open on one end. Such tracks can sometimes act as an antenna and that is not good.

The track with these green dots can also be moved to the red layer.

@Spaceboy

Can you suggest some ways to improve my board? Do I have to increase its size and put all components on top?

In general it’s common practice to place the (main) GND plane on the opposite layer then the SMT footprints, so you also have a continuous GND plane under all the SMT footprints. This also reduces the amount of vias (routing effort) because signals are routed on the same layer as the SMT footprints. Especially in the area around the barrel jack you are loosing a bit of the GND reference because it’s on the same layer as the SMT tracks. Now you have a via’s in (nearly) all signal lines which are leaving a group of SMT footprints. There is no need to change this now, but something to consider for your next PCB.

What is this big rectangular thing?

I guess it’s such a chinese SMPS module.

You already have a few electrolytic capacitors “sticking though” it. and mounting holes (are they for that module?

You can put SMT footprints under modules such as the arduino and (presumed) SMPS module. But do note that this makes it more difficult to do rework and repairs.

Some things to consider for all PCB’s: Add mounting holes to your project. Corners are not the ideal locations for mounting holes. The best locations are near connectors, especially screw terminals because those are locations where mechanical stress is introduced in to the PCB.

Put your name, date and project name on the PCB. It’s always nice to see a bit of promotion of KiCad (KiCad has some footprints with logos) and some text so you don’t forget (years later) which project (or which variant / revision of a project) it is is useful. When you want to make your project public, it’s also easier for others who see the PCB to find more info. For commercial projects you may also need other icons such as RoHS or the garbage can.

[Spaceboy]

Wow, thanks for your time!
The track in the first pictur is an analog one that is why I was shy about routing it near digital traces but I guess that distance of sepration as you’ve shown don’t matter much.
Also the vias to the smt components were done so that they go over as much of the GND plane on the red side as possible. But it does cross over power planes. So does GND vias next to them improve it?
And I didn’t understand what you meant my the losing of ground reference on the barrel jack.
Yes it is a buck boost. The capacitors will end up mounted underside (on the blue side)

[teletypeguy]

Yes, yes, and yes to everything Paul said, and don’t forget to add testpoints for all power supply voltages and any signals you will need to (or even maybe need to) probe as you are bringing up baby. For testpoints, one I often use is a 1.6mm pad with a 0.9mm hole and a silk circle around it. Scope probe tip snuggles in it nicely without sliding. I set up various TP sizes and sometimes I use larger or smaller testpoints, down to just a small smt pad for tight quarters.

Are there any unused pins you see yourself hacking wires on for future mods? Add some wire pads now. Unused micro pin or two can benefit from an open jumper to ground (0603 resistor works) so you set as input with internal pullup and read pin status at boot time. I use this for things like “DEV” mode where I output verbose messages to my serial port that don’t go in production. Solder or remove the jumper as needed. Just think about how you could see hacking the board and do your future self a favor or two now. Any signals that could benefit from an led? Now’s a good time. Don’t forget a power led.

Also a scope ground – I like to use a 1x2 100mil header near the edge of the board (and perpendicular so the ground clip sticks out of the board).

When you think you are all done, spend some time to peek at silkscreen again and scoot things around so ref-des and other text are not over vias (chops up the text), in the middle of a component (and not visible after assembly), etc. It is also helpful to use the 3d viewer to get a different perspective on silk. Don’t forget bottom silk where you have oodles of space for extra info (maybe notes on jumper positions…).

For ref-des silk I use 0.64x0.64x1.5mm, and for bonus text (labels on connectors, testpoints…) I use 1x1x0.25mm italic. A white square or rectangle (I always put one next to my board number) gives you a place to write with a sharpie to perhaps ID several boards (X, Y, Z) you built with different opamps and will do noise floor tests, or something like that. A larger rectangle (perhaps on bot silk) will give you a place to write bigger IDs like “Proto-A” or whatnot. An example silk, fwiw:

[paulvdh]

Analog signal conditioning is a whole chapter of a thick book on it’s own. When you are forcing return currents from digital signals to detour because you made a cutout in the GND plane (by your analog track), then the return currents will hug that track, and thus cause a much greater disturbance in the analog signal. Robert Feranec has made some good video’s with visulalizations of how return currents in GND paths behave.

@Spaceboy

And I didn’t understand what you meant my the losing of ground reference on the barrel jack.

I probably made an error here. I was a bit confused by the big cutouts in your GND plane by some tracks:

But it looks like there is no other GND in that corner. I’m also not sure what those SMT parts near that connector are doing.

@Spaceboy

The capacitors will end up mounted underside (on the blue side)

This is not good. It looks like those capacitors are the only things sticking out from the underside of the PCB. It makes it more difficult to mount the PCB, and they easily get damaged. You can move the barreljack a bit lower and put C1 on the place where the barrel jack is now. C2 can also be moved to just next to the module. Putting those electrolytics too close to the edge though, also makes it more likely they get damaged. I don’t know what those SMT parts do. Electrolytic buffer capacitors in general have quite high parasitic inductance. They are good for low frequency decoupling, but you may need ceramic decoupling capacitors too. But I can’t tell from the limited info I have.

I also make mistakes. I missed you already put a nice fat Organ-On-A-Chip title on the PCB

[Spaceboy]

Well yeah that smt next to the big cap on the input side is a 0.1uF ceramic. All SMT in the top are just for switching purposes of the MOSFETs which in turn switch several components. And it will be just placed side wise into a 3d printed container (not bottom down, but side down). Might increase size of the board to bring both a apcitors up top if that is an issue. But I guess I can’t move the second cap to the left because it needs to filter out the buck output and couple the buck output power plane with ground

[paulvdh]

Location of electrolytics is not very critical. If you wish you could add a net tie here. In that case, connect the output of the buck converter directly to the capacitor, and then a net tie to in between the capacitor connection and the power symbol. This will force all ripple current to go very close to the capacitor.

But I’m doing guesswork here. You don’t have to move the capacitors. It’s perfectly fine to leave them where they are now. At most they become a small nuisance in the “mechanical” aspect of the project.

[Spaceboy]

Interesting, never heard of net ties before. If possible, can you please show me an example or a visualization of what you meant?

[paulvdh]

One of the classical examples for net ties is a kelvin connection to a current measuring shunt resistor. The location of the shunt is often sort of fixed to reduce voltage drop and PCB area used for the wide high current traces, and the feedback signals are taken directly from the pads of the resistor, so voltage drop over PCB tracks is not a part of the feedback signal.

There are plenty of example out there for net ties “out there” already.

[Piotr]

@Spaceboy

Can you suggest some ways to improve my board?

After 3 hours driving (from 1.am till 4.am), waiting while the tea is getting cold, I decided to look into KiCad forum. I was too tired and sleepy to exercise my mind by analyzing your PCB.
The consequence is that today I got to work after 1 p.m. Before getting back to my urgent tasks (last time I have few things with term ‘for yestarday’) I get a short look at forum, but will no analyse your PCB. Sorry. I think I gave you a fishing rod and you can catch fish yourself.
Not reading paulvdh answers I can confirm that they certainly are best you can get.