Are you designing with multi-hundred pin FPGAs? Do you need to highlight all the I/O pins in bank 2 that are in the 3 outermost columns so you can decide which pins should hook to what? PadPainter does that. And more.
Now that looks nifty !
There is still some debate around Pin/group swapping (see other threads) - maybe V6 ?
How hard is it to add a menu subfield for pins/groups to swap ?
I envision you run it once to see what’s possible, then decide to swap a few.
User enters the pins to swap, in some list form, or even picks from a list ?
In parts like resistor networks, you want group swap - aka paired pinswap.
I got the same error a few days ago. I just pushed a fix to Github.
The WireIt tool is what I use to swap pins, but it’s done on a pin-by-pin basis. Group swapping is harder to envision unless you do it as a strict unit-to-unit swap like with resistor networks.
'rebuild board connectivity' what exactly does it try to do?
Pads changed to Vias on Gerber to PCB export
Using pcbnew without netlist
Wow, now that is brilliant.
You could add that shift-clk is how to select 2 pads ready for swap.
It seems to swap routed pins just fine too, so the ‘swap airwires between two pads’ is verbose and not quite accurate.
Maybe hint of ‘Pinswap netnames’ is shorter and more accurate ?
Playing with it, it says ‘connect pads with an airwire’ and icon shows 2 pads.
but it’s actually smarter than that, you can ‘apply Netname to N Selected Pads’ using this, and if any on those N already has a NetName it applies that.
I’d suggest change the hint to the more powerful ‘apply Netname to N selected pads’
Likewise ‘disconnect airwires from pads’ is ‘remove Netname from N selected pads’
Airwires / ratsnests auto-follow the net names.
There is no path I can see to edit a netname ? eg if you make a typo, and need to correct
Can that be added ?
Currently it brick-walls on merge of nets, can that enhance to give the choice to use either name ?
(ie allow net merge?) Some CAD flows give the 3rd choice of enter-net name when merging nets.
The ability to edit net name would permit that in 2 steps.
Dump to file give access error if I type a simple name. It seems to not use the PCB directory as default ?
The report file looks like
Part J1: Pad 5 moved from Net (0) to Net fixname (12).
Part J1: Pad 8 moved from Net (0) to Net /NTH (2).
Part J4: Pad 3 moved from Net (0) to Net Net-(J1-Pad3) (3).
Part J4: Pad 6 moved from Net (0) to Net /NTH (2).
Can that add a line for the Design file these changes applied to, and maybe a default swap file name can be suggested, derived from the Design File ? (avoids everyone inventing new names…)
What does the (12) (2) etc suffix numbers mean ?
Another small enhancement suggestion for the ‘apply net name’ feature.
If you select N-Pads and >= 1 NET segment, can it ‘seed’ the NET name, from that selected segment ?
Currently, if it finds a net name, on any PAD, it applies that. This extends that IQ very slightly, to checking if anything selected has a net name.
Currently, this is pin-focused, but I’ve seen cases where a new footprint was added, or traces imported with NET names, and then a KiCad footprint swapped. Pin+Segment select to attach net names, allows higher zoom levels to be used.
For porting designs from other CAD tools, it is simpler to export traces/nets than fully translate footprints.
These are good ideas. Most of them. I think.
It would probably be helpful to have you add them as issues in Github so they don’t get lost in the forum. I’ll work on them as I get the chance.
As for the output to the report file, the nets are denoted using their net name (a string) and net code (an integer) because some nets don’t have an actual string name (such as net 0, the net of unconnected pads).
Ah…ok, the location of the number at then end had me fooled a little.
The pcbnew file has this format for net names
(net 0 “”)
(net 1 “Net-(C1-Pad2)”)
so you could modify your report slightly to become
Part J1: Pad 8 moved from net 0 “” to net 1 “Net-(C1-Pad2)”
Part J1: Pad 8 moved from (net 0 “”) to (net 1 “Net-(C1-Pad2)”)
The last one exactly matches the KiCad PCB net format, so parsers could work on this.