How does this oscillator composed of not gates simulate?
I loaded the simulation model for 74HC04, but could not add V(OUT) probe!
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Where did you obtain the simulation model? Please post the link here.
The ngspice error message tells me that the setup ‘symbol/spice simulation model’ is not made correctly. There is some action required, when using multi-part units (e.g. 6 inverters in one package). See KiCad Eeschema as GUI for ngspice, tutorial for setting up the simulation for an (analog) example.
Be careful if you are thinking of really using this.
- My recent experience was with something more like a 74LVC2G14 (schmitt trigger inverter) but:
- I think there is similarity in that:
- When the voltage into the gate is in the threshold region (maybe 2V-3V instead of a clean logic “0” or “1”) the supply current goes way up. I had a single schmitt inverter running as an oscillator; it was drawing about 20 mA (+5V supply) so 100 mW. This may be OK for experimentation but I would not recommend it for a production design.
I like to use a comparator oscillator when possible. Most comparators are not as fast (I think your oscillator is not high frequency anyway) and may be less convenient, but is very stable and predictable.
You’re not supposed to use 74xx04 or 74xx14 for these types of oscillators. They make a special version of the 74xx04 with a ‘U’ in it (e.g. 74HCU04) which indicates it’s unbuffered and can used in crystal oscillator and astable multivibrator designs. See page 7 & 8 of this datasheet:
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Holy smokes…OK…learn something…but when I search “74HCU04” at Digikey it is almost not available.
https://www.digikey.com/en/products/detail/micross-on-semiconductor/74HCU04/5137793
I note that the CD4000 series has a lot of B and (non B) components, but I am disinclined to use the old CD4000 series with 5V just because it is such an old series; I guess it should work OK.
But my oscillator used one inverter. I believe that only works with a schmitt trigger input. The oscillator simply had a resistor from input to output and a capacitor from input to ground. This oscillator is even shown on a datasheet…I will edit this post later to add a link if I can find that datasheet.
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Being old, they tend to run out of puff around 1MHz. You can give them a bit of 10V viagra to improve matters somewhat. 
The capacitor swings between the upper and lower trip points of the schmitt trigger. If you use a two input gate eg. nand schmitt, you can use the other input as an on/off switch.
Geezz this stuff is stirring up the memories. 
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OK my oscillator is per Figure 16 on this datasheet.
I think I see 2 different issues.
That is what my oscillator does; the potential issue is high supply current. I have seen a graph supporting this on yet a different datasheet.
See Figure 9 on this one:
The OP oscillator relies on R1 & internal ESD diodes to limit the peak voltage into the input of the first inverter. But I would think that pretty much all ICs (not just the UB versions of CMOS logic) have such ESD protection to protect the IC from the gremlins of our world.
Does this make sense or am I spouting CMOS illogic?
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I know for given res. & cap. values, the schmitt astable will produce a much higher frequency than the two gate astable. I think it was around X4 faster. This is because the voltage swing is much smaller (schmitt trigger thresholds are closer to each other than the ESD diode thresholds).
They all had ESD diodes but the original A series had no buffer. The buffer is a pair (or more, some have 3 pairs) of inverters on the output to improve symmetry and shape of the gate output. These are the “B” series.
That 74HCU04 is like the As. I suppose it is all about propagation delays because of the buffering on the outputs, but I stand to be corrected.
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An inverter chain with an odd number of stages, output fed back to the input, with optional buffer stage for achieving a digital output, is known as a Ring Oscillator.
Some pratical approach:
Download a spice model, e.g. from https://www.ti.com/product/SN7404#design-development .
This model seems to be overly complex, but o.k.
A ngspice test circuit (standard ngspice) is this: Three inverter stages with feedback and output buffer, useful transient simulation conditions and (important for oscillators) a suitable starting condition:
Ring Oscillator with 7404
VCC1 vcc 0 5
.include SN7404.cir
* Three inverter stages
* .SUBCKT SN7404 Y A VCC AGND
* Three RO stages
XINV1 out1 in1 VCC GND SN7404
XINV2 out2 out1 VCC GND SN7404
XINV3 in1 out2 VCC GND SN7404
* Output buffer
XINV4 bufout in1 VCC GND SN7404
* required to set a starting condition
.ic v(in1)=5
.tran 10n 1000n uic
.control
run
set xbrushwidth=2
plot bufout
plot -vcc1#branch ylimit 0 5m ylabel 'current consumption'
.endc
.end
EDIT: Add plot for current consumption:
What to do when using Eeschema, will follow.
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Simulation with Eeschema
Place units, make connections:
If not all units are required, put them aside, set the input to GND (might or might not be necessary, depending on the model.
Global labels have been used to avoid name mangling (prepended / or unconnected pin). This is o.k. for simulation only. Add a text field with the .tran command and the .ic command (osc. start condition).
Create a new ngspice subcircuit model, including all 6 inverters. The nodes are in the sequence 1 to 14, taking correct inputs and outputs into account, so no alternate node sequence is required.
*7404subckt.lib
* symbol node sequence taken into account
.subckt 7404comp i1 o1 i2 o2 i3 o3 GND o4 i4 o5 i5 o6 i6 vcc
.include SN7404.cir
XINV1 o1 i1 VCC GND SN7404
XINV2 o2 i2 VCC GND SN7404
XINV3 o3 i3 VCC GND SN7404
XINV4 o4 i4 VCC GND SN7404
XINV5 o5 i5 VCC GND SN7404
XINV6 o6 i6 VCC GND SN7404
.ends
Put this subcircuit into a file 7404xxx.lib. Attach the subcircuit to each unit (including the power unit). This is somewhat annyoing, people are working on it for KiCad 7.
Run the simulation.
7404.7z (7.4 KB)
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What are the steps you did to get this result?
I just open the file you uploaded, click Run Simulation, and add the probe
Go to
Inspect → Simulator → Sim Parameters → Compatibility mode → PSPICE and LTSPICE
Then run the simulation.
I think CMOS has some historisous on the inputs. Kind of a Schmitt trigger. Like you said it’s along time ago.
I think this application note will bring some enlightenment:
CMOS oscillator_AN-118.pdf (84.2 KB)
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Would anything make you sit or lie down? 
There is yet another inverter oscillator I made many years ago. This one would be highly illegal (component stress) but it worked with (I think) a 74S or 74LS bipolar inverter. This was an LC oscillator. It had something like 1 nF from output to ground, 3.3 nF from input to ground, and maybe 10 turns of hookup wire wound around a pencil connected from input to output. I would not expect the chip to last long operating like that, but it did operate as an experiment.
Indeed, I am no longer darkened! Interesting article!
Yes, and dated 1974. We all probably read it about 45 years ago!!!
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The date I see on the linked document is 1998 although that might not be the oldest version. I note that they discuss logical oscillators but not illogical ones. I wonder how many are really logical…in that they do not draw too much power, and are stable and predictable enough to be used in a product.
Not so long ago I took an inverting gate driver with schmitt input, and used it as an oscillator to drive a charge pump to make a negative voltage with a few mA of current capability. But I also injected a clock so that it would synchronize when the clock was available. The thing I may have missed is the same issue of high supply current. Well, that design did not make it to production anyway…