I’m routing a BGA with 0.8mm pitch and 0.4mm diameter pads (created as per the datasheet).
I set the Pad Clearance on the footprint properties to 0.12mm to allow for an escape via or a single 0.1524mm (6mil) trace between the pads.
I have created net classes for my signals, many of which connect to BGA pads. The bulk of the signals are in the main net class with 0.1524mm (6mil) clearance and minimum track width.
The problem is, when I try to route a BGA pad the escape via is not allowed (violates the net class) because the pad seems to inherit the net class clearance (0.1524mm) instead of using the value I have set for the footprint (0.12mm).
The only way I have found to make this work is to set the net class to 0.12mm clearance and route the BGA escape vias, then change the net class back to 0.1524mm clearance so I can route the remainder of the trace on the board. The problem with this is, now when I run the DRC all the BGA pads show clearance errors.
This is very frustrating. Am I missing something, or is this a bug?