That makes sense, pads should not override net classes of traces being routed near them, but I'm talking about the pads themselves inheriting the net class clearance instead of using the value set in the footprint.
Attached are two screen shots. The first could only be routed when the net class for the HSWAP signal (which connects to pad B2) was set to match the footprint clearance of 0.12mm. If I set the desired net class clearance of 0.1524 for the class that HSWAP belongs to, then you can see in the second screen shot that pad B2 is pushing the via up and right because the pad itself is using the net class clearance of the signal connected to it (and B2 is not even routed yet). Also note that the clearance for the +3V3, GND and unused pins net class is set to 0.0001mm in this case to be sure it is not causing the problem.
It seems to me that that pads should not do this. If pads inherent the net class clearance of any signals connected to them, then what is the purpose of the pad clearance in the first place?
I think other PCB software fixed this by having multiple separate clearance settings in each net class for things like pad-to-pad, via-to-pad, via-to-trace, trace-to-pad, and trace-to-trace. In my case, after routing, all nets with vias under the BGA fail the DRC because the via-to-pad clearance needs to be that of the footprint (0.12mm), yet the vias get the trace net class clearance value of 0.1524mm.
I thought about the net-tie work-around, however can I have a net-tie that does not require a physical footprint? Logical net class separation is all I need / desire in this case.