Protip #2: net tie

KiCad doesn’t support net ties any more than it supports via stitching, but you can force it to.

It’s quite simple to do: make a footprint with two pads, far enough apart not to cause clearance issues, and then draw a graphic line between them to link them. DRC ignores the line, so there’s no clearance violation. It’s a good way to link together nets that you want connected in a controlled manner.

For anyone who wants to see them in practice:

Using a net tie in KiCad:
Making a net tie in KiCad:

Apologies for the potato microphone, I’ll try to improve the sound quality next time - but it’s better than the last, which had no audio at all!

My footprints and symbol:


So the key for using conductive paths in Kicad that would otherwise violate drc is to use graphical elements vs actual traces.

In a controlled manner, ideally, via a specific footprint…if you start drawing traces with the line tool I will tar and feather you >_>

You can’t draw traces in the footprint editor anyway since there are no nets to attach to.

I don’t know if it’s the same thing, but I needed a way to add a jumper in the schematic (actually a 0R resistor to cross tracks on a single layer SMD board). The trick I came up with was to add the resistor but also add a schematic trace to short the two sides. Worked great! PCBnew added a footprint for the resistor, but it didn’t split the net.

Yup, I’ve also done this.

if you start drawing traces with the line tool I will tar and feather you >_>

You can’t draw traces in the footprint editor anyway since there are no nets to attach to

Not what I meant. You’re both reading way more into my comment than than was intended.

I was just kidding :wink:

Thanks, I never thought of that but it seems so obvious now - silly me, and I even know about how the net code works since I’ve read it so many times.

How can you get around DRC on the PCB? It will list the pads of the link as unconnected. Won’t it?

Well, I seem to be passing DRC checks, so that doesn’t seem to be a problem. Remember that the netlist says that both sides are the same net, so maybe that means they’re connected.

Felippe, The graphic portion of the footprint is not seen as a conductive path by the drc, whereas a section of trace is. That is the key detail that makes this work. The netlist connections are otherwise unaffected.


A big thanks for this, I’d been thinking this morning how to achieve this and then searched and found your post. :slight_smile:

I can imagine there might be some circumstances when using a net tie may be beneficial, however for the board that you showcased in your video it would be much better to insert a keep out area over the trace to prevent ground pour covering the trace. Net tie is not a standard schematic symbol and reduces readability of the schematic, especially if you have several of them. Another con of this approach is that you can’t highlight the whole net anymore, which is not a big deal in your example but can become a problem in bigger designs.

Do you have a better idea, given the lack of a builtin component that provides the needed function?

Better idea for what? As I said before, I can think of a scenario when suggested solution may come useful, but in the case highlighted by the video a simple keep out would suffice.

Really, really late to reply, but I’ll do it for the sake of anyone reading this in the future:

Net ties have some very solid advantages over using a keepout:

  • They allow the separation between nets to be specified at schematic capture time, which is when the necessity of it is often first known.
  • They allow a net to be specified to be separate from itself, which a keepout cannot do. If you have e.g. a current sense resistor with fat power traces going in and thin sense traces going out, a keepout will not prevent you from accidentally crossing a fat trace with a thin trace, or from connecting the thin traces at the wrong point (before the pad rather than after).

Also, while the specific symbol I used here is indeed not one of the traditional symbols, anyone who thinks they are uncommon in schematics has not seen any modern schematics.

Further…example cases are often simplified, so I don’t know the point of the “for the board that you showcased” complaint. I suspect just to complain.

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I’ve played Portal, and you sound NOTHING like the device powered by a potato.

You might need a new day job…

This worked fine on v4 (with nightly updates until the release of V5), but now I have clean install of V5 (with nightly updates) I cannot join the nets. A keepout is displayed around each pad and does not allow a connection. Cannot route in and trying to route out gives Warning “Cannot start routing inside a keepout area or board outline”. Anyone else come across this or know a work around. Thanks

Nowadays, in 5.0, KiCad has net tie symbols and footprints in the standard library. They work if they are used like other components. You can think them as 0 ohm resistors. Try them and tell if you still have problems.