Net class overrides pad clearance


To get back to the original problem, did you check with visible clearance lines which one actually has too large clearance? Here in 5.0RC1+ it’s clearly the via, not pads. Pads obey the given pad clearance.

Can you make the vias smaller?

If the vias are already as small as allowed, you could cheat a bit. Create a footprint with only a round(ish or octagonal) non-pad copper area of the diameter of the needed via diameter. Make the via annular ring smaller and place the footprint on it. The non-pad footprint copper area doesn’t offend DRC. For the power plane part of the via you have to e.g. use a thicker via segment.


@eelik, I don’t think the problem is the via in this case because when the via would violate the real-time DRC, KiCAD refused to even draw the via and all I get is a trace that runs out from under the BGA. See my two photos in the earlier post. The via is being pushed away from the B2 pin. It is hard to tell in 4.0.7 which clearance is being used for any given pad or trace due to the inheritance, but by swapping clearance values in the net classes and footprint, it seems the problem is the pad. Here is another screenshot of routing a via between pads that are not connected (which belong to a different net class with a very small clearance). There is not problem and the via is snapping properly to the middle.


I just tested 4.0.7 in a virtual machine… looks like the clearance outlines are visible only in the Default view mode. So, switch to Default view mode for a while. Choose Preferences->Display->Show Track Clearance:Always and Footprints:Show pad clearance. Then post a new screenshot. I say this because for readers it’s so much easier to see with eyes than understand something written, and for you it’s easier to see it directly instead of playing with numbers.


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